Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction
In chip design, it is crucial to identify timing critical components early on to preemptively fix any timing issues and avoid numerous design convergence iterations. However, obtaining this information requires one to run the time intensive physical design flows (synthesis, placement, etc.). To this end, we propose a machine learning approach to predict timing path delays at a granular level directly from RTL design, thereby avoiding the reliance on synthesis and placement. This will allow designers to quickly evaluate the delays of timing critical paths as well as the worst-case delay at an early stage. Experiment results show that our approach predicts timing path delays with 91% accuracy when compared with post-placement timing analysis. Furthermore, this approach identifies the specific logic sections in an RTL code responsible for the longest timing delay paths and is more than 40 times faster than the conventional synthesis and placement.
