Biologically Plausible Learning on Neuromorphic Hardware Architectures
Movement of model parameters from memory to computing elements in deep learning (DL) has led to a growing imbalance known as the memory wall. Neuromorphic computation-in-memory (CIM) is an emerging paradigm that addresses this imbalance by performing computations directly in analog memory. However, sequential backpropagation of error through a network in DL prevents efficient parallelization. A novel method, direct feedback alignment (DFA), resolves layer dependencies by directly passing the error from the output to each layer. This work explores the interrelationship of implementing a bio-plausible learning algorithm like DFA in-situ on neuromorphic CIM hardware, emphasizing energy, area, and latency constraints. Using the DNN+NeuroSim benchmarking framework, we investigate the impact of hardware nonidealities and quantization on algorithm performance, as well as how network topologies and algorithm-level design choices scale latency, energy, and area consumption of a chip. While standard backpropagation learns more accurate models when faced with hardware imperfections, DFA enables significant speedup through parallelization, reducing training time by a factor approaching N for N-layer networks.
