Effect of Capacitor Mismatch Nonlinearity on Inference Accuracy in Analog Compute-in-Memory Architectures
Compute-in-memory (CIM) accelerators enhance neural network performance with efficient multiply- accumulate (MAC) operations. While capacitive arrays are often leveraged for MAC in CIM designs, circuit non-idealities can degrade accuracy but commonly go unreported in the literature. In this paper, we present a framework to analyze the impact of nonlinearity, specifically capacitor mismatch, on two existing capacitive designs - C2C and binary-weighted - and propose another called split. The split design divides the capacitive array into two binary-weighted arrays with a unit capacitor. This configuration is more area-efficient than the weighted and less susceptible to capacitor mismatch than the C2C. Our results show that for a simple dataset (MNIST) and neural network (MLP), inference accuracy is not significantly affected by nonlinearity, with the C2C (least linear) achieving nearly the same accuracy as the weighted (most linear). However, for more complex datasets and neural architectures, the C2C exhibits a significant accuracy loss, achieving only 9.74%, while the split and weighted achieve 99.06% and 99.29%, respectively.
