Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology
Publication
, Journal Article
Srivastava, S; Rydell, F; Goens, A; Nagarajan, V; Sorin, DJ
Published in: IEEE Computer Architecture Letters
January 1, 2025
Traditional schemes for avoiding deadlocks compose techniques for both protocol deadlocks (virtual networks) and network deadlocks (virtual channels). Recent work has shown how to use fewer virtual networks by analyzing protocol stalls instead of just considering the longest chain of causally dependent messages. We identify a shortcoming in this work, which can lead to deadlocks, and show that combining stall analysis with analyses of message dependencies and topology can avoid deadlocks while using fewer buffers than the conventional approach.
Duke Scholars
Published In
IEEE Computer Architecture Letters
DOI
EISSN
1556-6064
ISSN
1556-6056
Publication Date
January 1, 2025
Volume
24
Issue
2
Start / End Page
305 / 308
Related Subject Headings
- Computer Hardware & Architecture
Citation
APA
Chicago
ICMJE
MLA
NLM
Srivastava, S., Rydell, F., Goens, A., Nagarajan, V., & Sorin, D. J. (2025). Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology. IEEE Computer Architecture Letters, 24(2), 305–308. https://doi.org/10.1109/LCA.2025.3618627
Srivastava, S., F. Rydell, A. Goens, V. Nagarajan, and D. J. Sorin. “Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology.” IEEE Computer Architecture Letters 24, no. 2 (January 1, 2025): 305–8. https://doi.org/10.1109/LCA.2025.3618627.
Srivastava S, Rydell F, Goens A, Nagarajan V, Sorin DJ. Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology. IEEE Computer Architecture Letters. 2025 Jan 1;24(2):305–8.
Srivastava, S., et al. “Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology.” IEEE Computer Architecture Letters, vol. 24, no. 2, Jan. 2025, pp. 305–08. Scopus, doi:10.1109/LCA.2025.3618627.
Srivastava S, Rydell F, Goens A, Nagarajan V, Sorin DJ. Efficient Deadlock Avoidance by Considering Stalling, Message Dependencies, and Topology. IEEE Computer Architecture Letters. 2025 Jan 1;24(2):305–308.
Published In
IEEE Computer Architecture Letters
DOI
EISSN
1556-6064
ISSN
1556-6056
Publication Date
January 1, 2025
Volume
24
Issue
2
Start / End Page
305 / 308
Related Subject Headings
- Computer Hardware & Architecture