Device-Algorithm Co-Design with FeFETs for On-device Continual Learning
Ferroelectric field effect transistors (FeFETs) are emerging as a compelling device for continual learning in edge systems due to their non-volatility, scalability, and energy efficiency. However, integrating continual learning algorithms, which are typically designed for ideal weights, into FeFET-based architectures is challenging due to limited conductance resolution and intrinsic stochasticity. These non-idealities often demand compensation circuitry, increasing area and energy overheads and undermining the device level benefits. To address this challenge, we propose a device-algorithm co-design that aligns brain-inspired continual learning with FeFET device physics. Specifically, we exploit stochastic switching in FeFETs to realize probabilistic bits (p-bits) to drive weight consolidation. The p-bits are integrated into a 1T-1FeFET crossbar to support parallel probabilistic updates for on-device continual learning. Our co-design approach reduces the circuit area for Bernoulli sampling by compared to a pseudo-RNG-based approach and lowers energy consumption by ∼72% for weight read/write operations, while maintaining comparable performance on two continual learning benchmarks.
