An evaluation of the impact of gate oxide tunneling on dual-V t -based leakage reduction techniques
Publication
, Journal Article
Oliver, LD; Chakrabarty, K; Massoud, HZ
Published in: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
January 1, 2006
We evaluate the effectiveness of dual-Vt design in the presence of both subthreshold leakage and leakage due to gate oxide tunneling. At the device level, we use detailed HSPICE simulation to investigate the total leakage impact of three methods of dual-Vt implementation: multiple channel doping, channel length, and oxide thickness. At the system level, we generate and characterize a standard cell library and apply three representative delay-constrained leakage minimization dual-Vt assignment algorithms to the ISCAS'85 combinational benchmark circuits. Results show that oxide thickness modulation effectively reduces total leakage power consumption, but channel doping and channel length modulation are less effective. Copyright 2006 ACM.
Duke Scholars
Published In
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
DOI
Publication Date
January 1, 2006
Volume
2006
Start / End Page
105 / 110
Citation
APA
Chicago
ICMJE
MLA
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Oliver, L. D., Chakrabarty, K., & Massoud, H. Z. (2006). An evaluation of the impact of gate oxide tunneling on dual-V t -based leakage reduction techniques. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2006, 105–110. https://doi.org/10.1145/1127908.1127935
Oliver, L. D., K. Chakrabarty, and H. Z. Massoud. “An evaluation of the impact of gate oxide tunneling on dual-V t -based leakage reduction techniques.” Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 2006 (January 1, 2006): 105–10. https://doi.org/10.1145/1127908.1127935.
Oliver LD, Chakrabarty K, Massoud HZ. An evaluation of the impact of gate oxide tunneling on dual-V t -based leakage reduction techniques. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2006 Jan 1;2006:105–10.
Oliver, L. D., et al. “An evaluation of the impact of gate oxide tunneling on dual-V t -based leakage reduction techniques.” Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, vol. 2006, Jan. 2006, pp. 105–10. Scopus, doi:10.1145/1127908.1127935.
Oliver LD, Chakrabarty K, Massoud HZ. An evaluation of the impact of gate oxide tunneling on dual-V t -based leakage reduction techniques. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2006 Jan 1;2006:105–110.
Published In
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
DOI
Publication Date
January 1, 2006
Volume
2006
Start / End Page
105 / 110