ConferenceProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2023 · October 28, 2023
The increasing complexity of computer chips and the slow logic synthesis process have become major bottlenecks in the hardware design process, also hindering the ability of hardware generators to make informed design decisions while considering hardware co ...
Full textCite
ConferenceProceedings - 2023 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2023 · January 1, 2023
Embedded systems are becoming increasingly complex, which has led to a productivity crisis in their design and verification. Although conventional design automation coupled with IP and platform reuse techniques have led to leaps in design productivity impr ...
Full textCite
ConferenceProceedings - International Symposium on Computer Architecture · June 18, 2022
The number of transistors that can ft on one monolithic chip has reached billions to tens of billions in this decade thanks to Moore's Law. With the advancement of every technology generation, the transistor counts per chip grow at a pace that brings about ...
Full textCite
ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS · February 28, 2022
Protein language models have enabled breakthrough approaches to protein structure prediction, function annotation, and drug discovery. A primary limitation to the widespread adoption of these powerful models is the high computational cost associated with t ...
Full textCite
ConferenceNLP-Power 2022 - 1st Workshop on Efficient Benchmarking in NLP, Proceedings of the Workshop · January 1, 2022
With many real-world applications of Natural Language Processing (NLP) comprising of long texts, there has been a rise in NLP benchmarks that measure the accuracy of models that can handle longer input sequences. However, these benchmarks do not consider t ...
Full textCite
Journal ArticleIEEE Micro · May 1, 2021
This article presents a framework, Genesis (genome analysis), to efficiently and flexibly accelerate generic data manipulation operations that have become performance bottlenecks in the genomic data processing pipeline utilizing FPGAs-as-a-service. Genesis ...
Full textCite
ConferenceProceedings - International Symposium on Computer Architecture · May 1, 2020
In this paper, we describe our vision to accelerate algorithms in the domain of genomic data analysis by proposing a framework called Genesis (genome analysis) that contains an interface and an implementation of a system that processes genomic data efficie ...
Full textCite
ConferenceProceedings - 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019 · March 26, 2019
The amount of data being generated in genomics is predicted to be between 2 and 40 exabytes per year for the next decade, making genomic analysis the new frontier and the new challenge for precision medicine. This paper explores targeted deployment of hard ...
Full textCite
ConferenceProceedings of the Annual International Symposium on Microarchitecture, MICRO · December 14, 2016
Graphs are one of the key data structures for many real-world computing applications and the importance of graph analytics is ever-growing. While existing software graph processing frameworks improve programmability of graph analytics, underlying general p ...
Full textCite
Journal ArticleIEEE Micro · May 1, 2015
The Q100 uses hardware specialization to improve the energy efficiency of analytic database applications. The proposed accelerators are called database processing units. DPUs are analogous to GPUs, but where GPUs target graphics applications, DPUs target a ...
Full textCite
Journal ArticleACM Transactions on Computer Systems · September 23, 2014
Data partitioning is a critical operation for manipulating large datasets because it subdivides tasks into pieces that are more amenable to efficient processing. It is often the limiting factor in database performance and represents a significant fraction ...
Full textCite
ConferenceInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS · March 14, 2014
In this paper, we propose Database Processing Units, or DPUs, a class of domain-specific database processors that can efficiently handle database applications. As a proof of concept, we present the instruction set architecture, microarchitecture, and hardw ...
Full textCite
Journal ArticleIEEE Micro · January 1, 2014
Targeted deployment of hardware accelerators can improve the throughput and energy efficiency of large-scale data processing. Data partitioning is a critical operation for manipulating large datasets and is often the limiting factor in database performance ...
Full textCite
ConferenceProceedings - International Symposium on Computer Architecture · August 12, 2013
The global pool of data is growing at 2.5 quintillion bytes per day, with 90% of it produced in the last two years alone [24]. There is no doubt the era of big data has arrived. This paper explores targeted deployment of hardware accelerators to improve th ...
Full textCite
Journal ArticleIEEE Computer Architecture Letters · January 1, 2012
Hardware acceleration is a widely accepted solution for performance and energy efficient computation because it removes unnecessary hardware for general computation while delivering exceptional performance via specialized control paths and execution units. ...
Full textCite
ConferenceCASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems · November 16, 2001
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent evidence suggests that these efforts may be faltering as pipelining and ILP p ...
Full textCite
Journal ArticleConference Proceedings - Annual International Symposium on Computer Architecture, ISCA · January 1, 2001
The growth of the Internet as a vehicle for secure communication and electronic commerce has brought cryptographic processing performance to the forefront of high throughput system design. This trend will be further underscored with the widespread adoption ...
Full textCite
