Alvin R. Lebeck | Scholars@Duke

Alvin R. Lebeck
Professor of Computer Science

My interests span atoms to applications, with a foundation centered in computer architecture and systems. I enjoy a combination of interdisciplinary and conventional research.

Current Appointments & Affiliations

Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 2007
Core Faculty in Innovation & Entrepreneurship, Duke Innovation & Entrepreneurship, Initiatives 2019

Contact Information

Box 90129, Durham, NC 27708-0129
D308 Lev Sci Res Ctr, Durham, NC 27708
alvy@duke.edu (919) 660-6551
http://www.cs.duke.edu/~alvy

Background
Education, Training, & Certifications
- Ph.D., University of Wisconsin - Madison 1995
- M.S., University of Wisconsin - Madison 1991
- B.S., University of Wisconsin - Madison 1989
Previous Appointments & Affiliations
- Professor in the Department of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 2009 - 2022
- Associate Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 2003 - 2007
- Assistant Professor of Computer Science, Computer Science, Trinity College of Arts & Sciences 1996 - 2002
- Assistant Professor of Electrical and Computer Engineering, Electrical and Computer Engineering, Pratt School of Engineering 1996 - 1999
Recognition
In the News
- DEC 31, 2020
  
  Thermo Fisher Scientific Acquires Programmable Dye Platform Pioneer Phitonex
- APR 14, 2020
  
  Phitonex Pushes the Envelope of Immunology Research with 40 Color Flow Cytometry Experiment
- OCT 10, 2019
  
  Phitonex Announces $2M Seed Funding
Awards & Honors
Expertise
Subject Headings
Research
Selected Grants
- CSR: Small: Improving Cloud Services by Exploiting Synchronized Clocks and Software Defined Flash awarded by National Science Foundation 2016 - 2021
- Accelerating Markov Chain Monte Carlo Inference awarded by Intel Corporation 2018 - 2021
- XPS: CLCCA: Collaborative Research: Harnessing Highly Threaded Hardware for Server Workloads awarded by National Science Foundation 2013 - 2019
- Molecular-scale Energy Transport and Computational Phenomena Enabled by DNA Nanotechnology awarded by Office of Naval Research 2014 - 2018
- Stochastic Computing Machines Enabled by DNA Self-Assembly awarded by Defense Advanced Research Projects Agency 2013 - 2016
- Collaborative Research: Circuit and Systems Architectures for Self-Assembled Nanoscale Computers awarded by National Science Foundation 2007 - 2011
- EMT: Expanding the Computing Domain with Self-assembled Nanophotonics awarded by National Science Foundation 2008 - 2010
- ITR: Nanoarchitecture: Balancing Regularity, Complexity, and Defect Tolerance using DNA for Nanoeletronic Integration awarded by National Science Foundation 2003 - 2007
- Architectural Support for Service Level Agreements awarded by National Science Foundation 2003 - 2007
- Main Memory Power Management awarded by National Science Foundation 2002 - 2006
- Managing Energy as a First Class Operating System Resource awarded by National Science Foundation 2002 - 2005
- Data-Intensive Computing for Spatial Models awarded by National Science Foundation 1999 - 2004
- CISE Research Instrumentation: System Support for Mobile and Embedded Workloads awarded by National Science Foundation 2000 - 2004
- ITR/SII/Systems Support for Energy Management in Mobile and Embedded Workloads awarded by National Science Foundation 2000 - 2002
- Informed Caching Environment awarded by National Science Foundation 1997 - 2002
- TUNE: System Support for Memory-Friendly Programming awarded by National Science Foundation 1997 - 2001
- TUNE: System Support for Memory-Friendly Programming awarded by National Science Foundation 1997 - 1998
External Relationships
- Microsoft Corporation
- Parehelia Bio
- Thermo Fisher Scientific / Phitonex, Inc.
Publications & Artistic Works
Selected Publications
- Books
  - Dwyer, Christopher L., and Alvin R. Lebeck. Introduction to DNA Self-assembled Computer Design. Artech House, 2008.
- Academic Articles
  - Snyder, J., A. R. Lebeck, and D. Zhuo. “RDMA Congestion Control: It Is Only for the Compliant.” Ieee Micro 43, no. 1 (January 1, 2023): 76–82. https://doi.org/10.1109/MM.2022.3208746.
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  - Bashizade, Ramin, Xiangyu Zhang, Sayan Mukherjee, and Alvin R. Lebeck. “Accelerating Markov Random Field Inference with Uncertainty Quantification.” Corr abs/2108.00570 (2021).
  - Misra, Pulkit A., Srihari Radhakrishnan, Jeffrey S. Chase, Johannes Gehrke, and Alvin R. Lebeck. “Lightweight Inter-transaction Caching with Precise Clocks and Dynamic Self-invalidation.” Corr abs/2003.04150 (2020).
  - Zhang, Xiangyu, Ramin Bashizade, Yicheng Wang, Cheng Lyu, Sayan Mukherjee, and Alvin R. Lebeck. “Beyond Application End-Point Results: Quantifying Statistical Robustness of MCMC Accelerators.” Corr abs/2003.04223 (2020).
  - LaBoda, Craig D., Alvin R. Lebeck, and Chris L. Dwyer. “An Optically Modulated Self-Assembled Resonance Energy Transfer Pass Gate.” Nano Letters 17, no. 6 (June 2017): 3775–81. https://doi.org/10.1021/acs.nanolett.7b01112.
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  - Laboda, C., C. Dwyer, and A. R. Lebeck. “Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic.” Ieee Micro 37, no. 4 (January 1, 2017): 52–62. https://doi.org/10.1109/MM.2017.3211112.
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  - Wang, S., A. R. Lebeck, and C. Dwyer. “Nanoscale Resonance Energy Transfer-Based Devices for Probabilistic Computing.” Ieee Micro 35, no. 5 (September 1, 2015): 72–84. https://doi.org/10.1109/MM.2015.124.
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  - Pang, J., C. Dwyer, and A. R. Lebeck. “More is less, less is more: Molecular-scale photonic NoC power topologies.” International Conference on Architectural Support for Programming Languages and Operating Systems Asplos 2015-January (March 14, 2015): 283–96. https://doi.org/10.1145/2694344.2694377.
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  - Pang, Jun, Christopher Dwyer, and Alvin R. Lebeck. “mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices.” Acm Journal on Emerging Technologies in Computing Systems 12, no. 1 (2015). https://doi.org/10.1145/2700241.
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  - Pang, J., A. R. Lebeck, and C. Dwyer. “Modeling and simulation of a nanoscale optical computing system.” Journal of Parallel and Distributed Computing 74, no. 6 (January 1, 2014): 2470–83. https://doi.org/10.1016/j.jpdc.2013.07.006.
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  - Pang, J., C. Dwyer, and A. R. Lebeck. “Exploiting emerging technologies for nanoscale photonic Networks-on-Chip.” Sixth International Workshop on Network on Chip Architectures (Nocarc 13), 2013, 53–58.
  - Romanescu, B., A. Lebeck, and D. J. Sorin. “Address translation aware memory consistency.” Ieee Micro 31, no. 1 (January 1, 2011): 109–18. https://doi.org/10.1109/MM.2010.99.
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  - Zhang, M., A. Lebeck, and D. Sorin. “Fractal consistency: Architecting the memory system to facilitate verification.” Ieee Computer Architecture Letters 9, no. 2 (July 1, 2010): 61–64. https://doi.org/10.1109/L-CA.2010.18.
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  - Pistol, Constantin, Vincent Mao, Viresh Thusu, Alvin R. Lebeck, and Chris Dwyer. “Encoded multichromophore response for simultaneous label-free detection.” Small (Weinheim an Der Bergstrasse, Germany) 6, no. 7 (April 2010): 843–50. https://doi.org/10.1002/smll.200901996.
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  - Pistol, C., V. Mao, V. Thusu, A. R. Lebeck, and C. Dwyer. “Molecular logic gates: Encoded Multichromophore Response for Simultaneous Label-Free Detection Small 7/2010.” Small 6, no. 7 (March 26, 2010). https://doi.org/10.1002/smll.201090020.
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  - Liu, Y., C. Dwyer, and A. R. Lebeck. “Routing in self-organizing nano-scale irregular networks.” Acm Journal on Emerging Technologies in Computing Systems 6, no. 1 (March 1, 2010). https://doi.org/10.1145/1721650.1721653.
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  - Pistol, C., W. Chongchitmate, C. Dwyer, and A. R. Lebeck. “Architectural implications of nanoscale-integrated sensing and computing.” Ieee Micro 30, no. 1 (January 1, 2010): 110–20. https://doi.org/10.1109/MM.2010.9.
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  - Pistol, C., C. Dwyer, and A. R. Lebeck. “Architectural implications of nanoscale integrated sensing and computing.” International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, January 1, 2009, 13–24. https://doi.org/10.1145/1508244.1508247.
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  - Lebeck, A. R., and K. Chakrabarty. “Introduction to DAC 2007 special section.” Acm Journal on Emerging Technologies in Computing Systems 4, no. 3 (August 1, 2008). https://doi.org/10.1145/1389089.1389090.
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  - Pistol, C., C. Dwyer, and A. R. Lebeck. “Nanoscale optical computing using resonance energy transfer logic.” Ieee Micro 28, no. 6 (January 1, 2008): 7–18. https://doi.org/10.1109/MM.2008.91.
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  - Patwardhan, J., C. Dwyer, and A. R. Lebeck. “A self-organizing defect tolerant SIMD architecture.” Acm Journal on Emerging Technologies in Computing Systems 3, no. 2 (July 1, 2007). https://doi.org/10.1145/1265949.1265956.
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  - Pistol, C., A. R. Lebeck, and C. Dwyer. “Design automation for DNA self-assembled nanostructures.” Proceedings Design Automation Conference, December 1, 2006, 919–24. https://doi.org/10.1145/1146909.1147143.
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  - Patwardhan, J. P., V. Johri, C. Dwyer, and A. R. Lebeck. “A defect tolerant self-organizing nanoscale SIMD architecture.” International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, December 1, 2006, 241–51. https://doi.org/10.1145/1168857.1168888.
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  - Li, T., A. R. Lebeck, and D. J. Sorin. “Spin detection hardware for improved management of multithreaded systems.” Ieee Transactions on Parallel and Distributed Systems 17, no. 6 (June 1, 2006): 508–21. https://doi.org/10.1109/TPDS.2006.78.
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  - Park, S. H., C. Pistol, S. J. Ahn, J. H. Reif, A. R. Lebeck, C. Dwyer, and T. H. LaBean. “Finite-size, Fully-Addressable DNA Tile Lattices Formed by Hierarchical Assembly Procedures.” Angewandte Chemie 45 (2006): 735-739-735–39.
  - Patwardhan, J. P., C. Dwyer, A. R. Lebeck, and D. J. Sorin. “NANA: A nano-scale active network architecture.” Acm Journal on Emerging Technologies in Computing Systems 2, no. 1 (January 1, 2006): 1–30. https://doi.org/10.1145/1126257.1126258.
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  - Dwyer, C., A. R. Lebeck, and D. J. Sorin. “Self-assembled architectures and the temporal aspects of computing.” Computer 38, no. 1 (January 1, 2005): 56–64. https://doi.org/10.1109/MC.2005.34.
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  - Zeng, H., C. S. Ellis, and A. R. Lebeck. “Experiences in managing energy with ECOSystem.” Ieee Pervasive Computing 4, no. 1 (January 1, 2005): 62–68. https://doi.org/10.1109/MPRV.2005.10.
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  - Dwyer, C., V. Johri, M. Cheung, J. Patwardhan, A. Lebeck, and D. Sorin. “Design tools for a DNA-guided self-assembling carbon nanotube technology.” Nanotechnology 15, no. 9 (September 1, 2004): 1240–45. https://doi.org/10.1088/0957-4484/15/9/022.
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  - Yang, C. L., H. W. Tseng, C. H. Lee, and A. R. Lebeck. “Tolerating Memory Latency through Push Prefetching for Pointer-Intensive Applications.” Acm Transactions on Architecture and Code Optimization 1, no. 4 (January 1, 2004): 445–75. https://doi.org/10.1145/1044823.1044827.
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  - Fan, X., C. S. Ellis, and A. R. Lebeck. “The synergy between power-aware memory systems and processor voltage scaling.” Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 3164 (January 1, 2004): 164–79.
  - Thottethodi, M., A. R. Lebeck, and S. S. Mukherjee. “Exploiting global knowledge to achieve self-tuned congestion control for k-ary n-cube networks.” Ieee Trans. Parallel Distrib. Syst. (Usa) 15, no. 3 (2004): 257–72. https://doi.org/10.1109/TPDS.2004.1264810.
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  - Chatterjee, S., A. R. Lebeck, P. K. Patnala, and M. Thottethodi. “Recursive array layouts and fast matrix multiplication.” Ieee Transactions on Parallel and Distributed Systems 13, no. 11 (November 1, 2002): 1105–23. https://doi.org/10.1109/TPDS.2002.1058095.
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  - Hanlon, P. J., D. Chung, S. Chatterjee, D. Genius, A. R. Lebeck, and E. Parker. “The combinatorics of cache misses during matrix multiplication.” Journal of Computer and System Sciences 63, no. 1 (January 1, 2001): 80–126. https://doi.org/10.1006/jcss.2001.1756.
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  - Yang, Chia-Lin, B. Sano, and A. R. Lebeck. “Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructions.” Ieee Trans. Comput. (Usa) 49, no. 9 (September 2000): 934–46. https://doi.org/10.1109/12.869324.
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  - Srinivasan, S. T., and A. R. Lebeck. “Load latency tolerance in dynamically scheduled processors.” Journal of Instruction Level Parallelism 1 (October 1, 1999).
  - Lebeck, A. R., and D. A. Wood. “Active memory: A new abstraction for memory system simulation.” Acm Transactions on Modeling and Computer Simulation 7, no. 1 (January 1, 1997): 42–77. https://doi.org/10.1145/244804.244806.
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  - Lebeck, A. R., and D. A. Wood. “Cache Profiling and the SPEC Benchmarks: A Case Study.” Computer 27, no. 10 (January 1, 1994): 15–26. https://doi.org/10.1109/2.318580.
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  - Lebeck, A. R., and G. S. Sohi. “Request Combining in Multiprocessors with Arbitrary Interconnection Networks.” Ieee Transactions on Parallel and Distributed Systems 5, no. 11 (January 1, 1994): 1140–55. https://doi.org/10.1109/71.329673.
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  - Reinhardt, S. K., M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, and D. A. Wood. “The Wisconsin wind tunnel: Virtual prototyping of parallel computers.” Proceedings of the 1993 Acm Sigmetrics Conference on Measurement and Modeling of Computer Systems, Sigmetrics 1993, June 1, 1993, 48–60. https://doi.org/10.1145/166955.166979.
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  - Hill, M. D., J. R. Larus, A. R. Lebeck, M. Talluri, and D. A. Wood. “Wisconsin Architectural Research Tool Set.” Comput. Archit. News (Usa) 21, no. 4 (January 9, 1993): 8–10. https://doi.org/10.1145/165496.165500.
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- Book Sections
  - Dwyer, C., and A. R. Lebeck. “Chapter 8 Self-Assembled Computer Architectures,” 5:181–98, 2008. https://doi.org/10.1016/S1571-0831(07)00008-1.
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- Other Articles
  - Misra, Pulkit A., Jeffrey S. Chase, Johannes Gehrke, and Alvin R. Lebeck. “Multi-version Indexing in Flash-based Key-Value Stores.” Corr, December 2, 2019.
    Open Access Copy
  - Zhang, Xiangyu, Sayan Mukherjee, and Alvin Lebeck. “A Case for Quantifying Statistical Robustness of Specialized Probabilistic AI Accelerators (Accepted).” 2019 Ibm Ieee Cas/Eds – Ai Compute Symposium, October 2, 2019.
    Open Access Copy
  - Liu, Yang, Chris Dwyer, and Alvin R. Lebeck. “Combined Compute and Storage: Configurable Memristor Arrays to Accelerate Search.” Corr, 2016.
  - Hsiao, M., S. Shukla, M. Gokhale, and A. Lebeck. “Panel: Nano-computing - Do we need new formal approaches?” Proceedings Fourth Acm and Ieee International Conference on Formal Methods and Models for Co Design, Memocode’06, December 1, 2006.
- Conference Papers
  - Kong, X., J. Chen, W. Bai, Y. Xu, M. Elhaddad, S. Raindel, J. Padhye, A. R. Lebeck, and D. Zhuo. “Understanding RDMA Microarchitecture Resources for Performance Isolation.” In Proceedings of the 20th Usenix Symposium on Networked Systems Design and Implementation, Nsdi 2023, 31–48, 2023.
  - Snyder, J., and A. R. Lebeck. “Fast Convergence to Fairness for Reduced Long Flow Tail Latency in Datacenter Networks.” In Proceedings 2022 Ieee 36th International Parallel and Distributed Processing Symposium, Ipdps 2022, 1007–17, 2022. https://doi.org/10.1109/IPDPS53621.2022.00102.
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  - Zhang, X., R. Bashizade, Y. Wang, S. Mukherjee, and A. R. Lebeck. “Statistical robustness of Markov chain Monte Carlo accelerators.” In International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, 959–74, 2021. https://doi.org/10.1145/3445814.3446697.
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  - Zeng, H., C. S. Ellis, A. R. Lebeck, and A. Vahdat. “Currentcy: A unifying abstraction for expressing energy management policies.” In Proceedings of the General Track: 2003 Usenix Annual Technical Conference, 43–56, 2020.
  - Witchel, E., and A. Lebeck. “Message from the Program Chairs.” In International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, IV–V, 2019.
  - Misra, P. A., M. F. Borge, I. Goiri, A. R. Lebeck, W. Zwaenepoel, and R. Bianchini. “Managing tail latency in datacenter-scale file systems under production constraints.” In Proceedings of the 14th Eurosys Conference 2019, 2019. https://doi.org/10.1145/3302424.3303973.
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  - Bashizade, R., Y. Li, and A. R. Lebeck. “Adaptive simultaneous multi-tenancy for GPUs.” In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 11332 LNCS:83–106, 2019. https://doi.org/10.1007/978-3-030-10632-4_5.
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  - Zhang, X., R. Bashizade, C. LaBoda, C. Dwyer, and A. R. Lebeck. “Architecting a stochastic computing unit with molecular optical devices.” In Proceedings International Symposium on Computer Architecture, 301–14, 2018. https://doi.org/10.1109/ISCA.2018.00034.
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  - Razeen, A., A. Meijer, A. R. Lebeck, V. Pistol, D. H. Liu, and L. P. Cox. “SandTrap: Tracking information flows on demand with parallel permissions.” In Mobisys 2018 Proceedings of the 16th Acm International Conference on Mobile Systems, Applications, and Services, 230–42, 2018. https://doi.org/10.1145/3210240.3210321.
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  - Misra, Pulkit A., Jeffrey S. Chase, Johannes Gehrke, and Alvin R. Lebeck. “Enabling Lightweight Transactions with Precision Time.” In Acm Sigops Operating Systems Review, 51:779–94. Association for Computing Machinery (ACM), 2017. https://doi.org/10.1145/3093315.3037722.
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  - Wang, S., X. Zhang, Y. Li, R. Bashizade, S. Yang, C. Dwyer, and A. R. Lebeck. “Accelerating Markov Random Field Inference Using Molecular Optical Gibbs Sampling Units.” In Proceedings 2016 43rd International Symposium on Computer Architecture, Isca 2016, 558–69, 2016. https://doi.org/10.1109/ISCA.2016.55.
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  - Agrawal, S. R., C. R. Dee, and A. R. Lebeck. “Exploiting Accelerators for Efficient High Dimensional Similarity Search (Accepted).” In Proceedings of the 21st Acm Sigplan Symposium on Principles and Practice of Parallel Programming, 2016.
  - Agrawal, S. R., V. Pistol, J. Pang, J. Tran, D. Tarjan, and A. R. Lebeck. “Rhythm: Harnessing data parallel hardware for server workloads.” In International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, 19–34, 2014. https://doi.org/10.1145/2541940.2541956.
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  - Zhang, M., A. R. Lebeck, and D. J. Sorin. “Fractal Coherence: Scalably verifiable cache coherence.” In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 471–82, 2010. https://doi.org/10.1109/MICRO.2010.11.
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  - Romanescu, B. F., A. R. Lebeck, and D. J. Sorin. “Specifying and dynamically verifying address translation-aware memory consistency.” In International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, 323–34, 2010. https://doi.org/10.1145/1736020.1736057.
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  - Romanescu, B. F., A. R. Lebeck, D. J. Sorin, and A. Bracy. “Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all.” In Proceedings International Symposium on High Performance Computer Architecture, 2010. https://doi.org/10.1109/hpca.2010.5416643.
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  - Romanescu, B. F., A. R. Lebeck, and D. J. Sorin. “Specifying and dynamically verifying address translation-aware memory consistency.” In Acm Sigplan Notices, 45:323–34, 2010. https://doi.org/10.1145/1735971.1736057.
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  - Liu, Y., and A. R. Lebeck. “Nano-scale on-chip irregular network analysis.” In Proceedings International Conference on Computer Communications and Networks, Icccn, 2009. https://doi.org/10.1109/ICCCN.2009.5235292.
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  - Pistol, C., W. Chongchitmate, C. Dwyer, and A. R. Lebeck. “Architectural implications of nanoscale integrated sensing and computing.” In Acm Sigplan Notices, 44:13–24, 2009. https://doi.org/10.1145/1508284.1508247.
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  - Patwardhan, J. P., C. Dwyer, and A. R. Lebeck. “Self-assembled networks: Control vs. complexity.” In 2006 1st International Conference on Nano Networks and Workshops, Nano Net, 2006. https://doi.org/10.1109/NANONET.2006.346222.
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  - Dwyer, C., S. H. Park, T. LaBean, and A. Lebeck. “The design and fabrication of a fully addressable 8-tile DNA lattice.” In 2nd Conference on Foundations of Nanoscience: Self Assembled Architectures and Devices, Fnano 2005, 186–90, 2005.
  - Li, T., C. S. Ellis, A. R. Lebeck, and D. J. Sorin. “Pulse: A dynamic deadlock detection mechanism using speculative execution.” In Usenix 2005 Annual Technical Conference, 31–44, 2005.
  - Patwardhan, J. P., A. R. Lebeck, and D. J. Sorin. “Communication breakdown: Analyzing CPU usage in commercial web workloads.” In 2004 Ieee International Symposium on Performance Analysis of Systems and Software, 12–19, 2004. https://doi.org/10.1109/ISPASS.2004.1291351.
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  - Li, T., A. R. Lebeck, and D. J. Sorin. “Quantifying instruction criticality for shared memory multiprocessors.” In Annual Acm Symposium on Parallel Algorithms and Architectures, 47–72, 2003.
  - Fan, X., C. S. Ellis, and A. R. Lebeck. “Modeling of DRAM power control policies using deterministic and stochastic petri nets.” In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2325:130–40, 2003. https://doi.org/10.1007/3-540-36612-1_9.
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  - Li, T., A. R. Lebeck, and D. J. Sorin. “Quantifying instruction criticality for shared memory multiprocessors.” In Annual Acm Symposium on Parallel Algorithms and Architectures, 128–37, 2003. https://doi.org/10.1145/777412.777434.
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  - Thottethodi, M., A. R. Lebeck, and S. S. Mukherjee. “BLAM: A high-performance routing algorithm for virtual cut-through networks.” In Proceedings International Parallel and Distributed Processing Symposium, Ipdps 2003, 2003. https://doi.org/10.1109/IPDPS.2003.1213133.
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  - Yang, C. L., and A. Lebeck. “A programmable memory hierarchy for prefetching linked data structures.” In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2327 LNCS:160–74, 2002. https://doi.org/10.1007/3-540-47847-7_15.
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  - Zeng, H., C. S. Ellis, A. R. Lebeck, and A. Vahdat. “ECOSystem: Managing energy as a first class operating system resource.” In International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, 123–32, 2002.
  - Zeng, H., C. S. Ellis, A. R. Lebeck, and A. Vahdat. “ECOSystem: Managing energy as a first class operating system resource.” In Operating Systems Review (Acm), 36:121–32, 2002.
  - Lebeck, A. R., J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. “A large, fast instruction window for tolerating cache misses.” In Conference Proceedings Annual International Symposium on Computer Architecture, Isca, 59–70, 2002. https://doi.org/10.1109/ISCA.2002.1003562.
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  - Chatterjee, S., E. Parker, P. J. Hanlon, and A. R. Lebeck. “Exact analysis of the cache behavior of nested loops.” In Sigplan Notices (Acm Special Interest Group on Programming Languages), 36:286–97, 2001. https://doi.org/10.1145/381694.378859.
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  - Chatterjee, S., E. Parker, P. J. Hanlon, and A. R. Lebeck. “Exact analysis of the cache behavior of nested loops.” In Proceedings of the Acm Sigplan Conference on Programming Language Design and Implementation (Pldi), 286–97, 2001.
  - Fan, X., C. S. Ellis, and A. R. Lebeck. “Memory controller policies for DRAM power management.” In Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 129–34, 2001. https://doi.org/10.1145/383082.383118.
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  - Srinivasan, S. T., R. D. C. Ju, A. R. Lebeck, and C. Wilkerson. “Locality vs. criticality.” In Conference Proceedings Annual International Symposium on Computer Architecture, Isca, 132–43, 2001. https://doi.org/10.1109/ISCA.2001.937442.
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  - Thottethodi, M., A. R. Lebeck, and S. S. Mukherjee. “Self-tuned congestion control for multiprocessor networks.” In Ieee High Performance Computer Architecture Symposium Proceedings, 107–18, 2001.
  - Vahdat, A., A. Lebeck, and C. S. Ellis. “Every joule is precious: The case for revisiting operating system design for energy efficiency.” In Proceedings of the 9th Workshop on Acm Sigops European Workshop: Beyond the Pc: New Challenges for the Operating System, Ew 2000, 31–36, 2000. https://doi.org/10.1145/566726.566735.
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  - Lebeck, A. R., X. Fan, H. Zeng, and C. Ellis. “Power aware page allocation.” In Sigplan Notices (Acm Special Interest Group on Programming Languages), 35:105–16, 2000. https://doi.org/10.1145/356989.356999.
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  - Yang, C. L., and A. R. Lebeck. “Push vs. pull: Data movement for linked data structures.” In Proceedings of the International Conference on Supercomputing, 176–86, 2000.
  - Lebeck, A. R. “Cache conscious programming in undergraduate computer science.” In Sigcse 1999 Proceedings of the 13th Sigcse Technical Symposium on Computer Science Education, 247–51, 1999.
  - Chatterjee, S., A. R. Lebeck, P. K. Patnala, and M. Thottethodi. “Recursive array layouts and fast parallel matrix multiplication.” In Annual Acm Symposium on Parallel Algorithms and Architectures, 222–31, 1999. https://doi.org/10.1145/305619.305645.
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  - Chatterjee, S., V. V. Jain, A. R. Lebeck, S. Mundhra, and M. Thottethodi. “Nonlinear array layouts for hierarchical memory systems.” In Proceedings of the International Conference on Supercomputing, 444–53, 1999. https://doi.org/10.1145/305138.305231.
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  - Lebeck, A. R. “Cache conscious programming in undergraduate computer science.” In Sigcse Bulletin (Association for Computing Machinery, Special Interest Group on Computer Science Education), 31:247–51, 1999. https://doi.org/10.1145/384266.299772.
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  - Lebeck, A. R., D. R. Raymond, C. L. Yang, and M. S. Thottethodi. “Annotated memory references: A mechanism for informed cache management.” In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 1685 LNCS:1251–54, 1999. https://doi.org/10.1007/3-540-48311-x_177.
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  - Srinivasan, S. T., and A. R. Lebeck. “Load latency tolerance in dynamically scheduled processors.” In Proceedings of the Annual International Symposium on Microarchitecture, 148–59, 1998.
  - Yang, C. L., B. Sano, and A. R. Lebeck. “Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications.” In Proceedings of the Annual International Symposium on Microarchitecture, 14–24, 1998.
  - Thottethodi, M., S. Chatterjee, and A. R. Lebeck. “Tuning Strassen's matrix multiplication for memory efficiency.” In Proceedings of the International Conference on Supercomputing, Vol. 1998-November, 1998. https://doi.org/10.1109/SC.1998.10045.
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  - Yocum, K. G., J. S. Chase, A. J. Gallatin, and A. R. Lebeck. “Cut-through delivery in trapeze: an exercise in low-latency messaging.” In Ieee International Symposium on High Performance Distributed Computing, Proceedings, 243–52, 1997.
  - Lebeck, A. R., and D. A. Wood. “Active memory: A new abstraction for memory-system simulation.” In Proceedings of the 1995 Acm Sigmetrics Joint International Conference on Measurement and Modeling of Computer Systems, Sigmetrics 1995/Performance 1995, 220–30, 1995. https://doi.org/10.1145/223587.223611.
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  - Lebeck, A. R., and D. A. Wood. “Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors.” In Acm Sigarch (Association for Computing Nachinery Special Interest Group on Computer Architecture) Conference Proceedings, 48–59, 1995.
  - Lebeck, A. R., and D. A. Wood. “Dynamic self-invalidation: Reducing coherence overhead in shared-memory multiprocessors.” In Conference Proceedings Annual International Symposium on Computer Architecture, Isca, 48–59, 1995.
  - Schoinas, I., B. Falsafi, A. R. Lebeck, S. K. Reinhardt, J. R. Larus, and D. A. Wood. “Fine-grain access control fcw distributed shared memory.” In International Conference on Architectural Support for Programming Languages and Operating Systems Asplos, Part F129531:297–306, 1994. https://doi.org/10.1145/195473.195575.
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  - Falsafi, B., A. R. Lebeck, S. K. Reinhardt, I. Schoinas, M. D. Hill, J. R. Larus, A. Rogers, and D. A. Wood. “Application-specific protocols for user-level shared memory.” In Proceedings of the Acm/Ieee Supercomputing Conference, 380–89, 1994. https://doi.org/10.1145/602770.602838.
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  - Wood, D. A., S. Chandra, B. Falsafi, M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, S. S. Mukherjee, S. Palacharla, and S. K. Reinhardt. “Mechanisms for cooperative shared memory.” In Conference Proceedings Annual Symposium on Computer Architecture, 156–67, 1993. https://doi.org/10.1145/165123.165151.
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  - Kessler, R. E., R. Jooss, A. Lebeck, and M. D. Hill. “Inexpensive Implementations Of Set-Associativity (Accepted).” In The 16th Annual International Symposium on Computer Architecture. IEEE, n.d. https://doi.org/10.1109/isca.1989.714547.
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- Technical Program Co-Chair. 24th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2019). 2019 2019

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