Photovoltaic multilevel inverter with distributed maximum power point tracking and dynamic circuit reconfiguration
This work will present a novel photovoltaic (PV) inverter with integrated short-term storage. The topology combines advantages of microinverter topologies, such as module-specific maximum-power-point tracking, failure-tolerance, safety due to limited voltages, modularity, use of low-cost low-voltage components such as silicon field-effect transistors (FET), and simple expandability, with those of conventional string inverters, such as low control electronics effort and high power conversion efficiency. Our approach substantially deviates from both microinverters, which connect small-scale module-dedicated inverters in parallel to feed into a common ac or dc interlink, and previously introduced modular multilevel converters (MMC) with integrated PV elements, which essentially wire a number of individual inverters in series. In contrast, we incorporate individual PV modules into power modules, which can dynamically reconfigure their series-parallel circuit configuration with their neighbors to generate the output. The individual power modules can use components with relatively low voltage and low cost. Each power module further incorporates a storage based on double-layer capacitors and NiMH batteries which provide a high power density. This short-term storage enables continuous power flow at the output and compensates input-power fluctuations, e.g., due to clouds. This approach provides exceptionally high output quality, beyond levels achievable with conventional two-level string inverters, since the dynamic rewiring between the power modules in mixed series-parallel configurations is operated at the switching speed of the FET switches so that ac sinusoidal output power is generated with fine quantization levels and furthermore pulse-width modulation between these levels is possible. Finally, the dynamic circuit reconfiguration for mixed parallel-series connectivity forms a near-ideal impedance converter that minimizes loss. The paper will validate and analyze the theoretical concept with an eight-module prototype based on state-of-The art low-loss silicon FETs.
