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Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs

Publication ,  Journal Article
Lin, YC; McGuire, F; Noyce, S; Williams, N; Cheng, Z; Andrews, J; Franklin, AD
Published in: IEEE Journal of the Electron Devices Society
January 1, 2019

Negative capacitance (NC) field-effect transistors (FETs) with 2-D semiconducting channels have become increasingly attractive due to their ability to produce sub-60 mV/dec switching behavior in a physically scalable device. However, it has yet to be determined how gate control, including threshold voltage, of 2-D NC-FETs is impacted by gate dielectric composition, along with dielectric and ferroelectric layer thicknesses. Here, we show the threshold voltage shifts positively under increasing ferroelectric thickness and negatively with increasing dielectric thickness. This shifting behavior is observed in devices without an interfacial metal layer between the ferroelectric hafnium zirconium oxide (HfZrO2 or HZO) and dielectric. Because the interface between the ferroelectric and dielectric is critical in driving NC behavior, we also study 2-D NC-FETs with 4 nm HZO paired with different dielectrics. These results reveal that the HZO/Al2O3 interface is more favorable than either the HZO/ZrO2 or HZO/HfO2 interfaces. Finally, the impact of an interfacial metal layer is discussed by comparing the 2-D NC-FET performance of similar devices with and without this layer.

Duke Scholars

Published In

IEEE Journal of the Electron Devices Society

DOI

EISSN

2168-6734

Publication Date

January 1, 2019

Volume

7

Start / End Page

645 / 649

Related Subject Headings

  • 4009 Electronics, sensors and digital hardware
  • 4008 Electrical engineering
  • 1007 Nanotechnology
  • 0906 Electrical and Electronic Engineering
 

Citation

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Lin, Y. C., McGuire, F., Noyce, S., Williams, N., Cheng, Z., Andrews, J., & Franklin, A. D. (2019). Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs. IEEE Journal of the Electron Devices Society, 7, 645–649. https://doi.org/10.1109/JEDS.2019.2922441
Lin, Y. C., F. McGuire, S. Noyce, N. Williams, Z. Cheng, J. Andrews, and A. D. Franklin. “Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs.” IEEE Journal of the Electron Devices Society 7 (January 1, 2019): 645–49. https://doi.org/10.1109/JEDS.2019.2922441.
Lin YC, McGuire F, Noyce S, Williams N, Cheng Z, Andrews J, et al. Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs. IEEE Journal of the Electron Devices Society. 2019 Jan 1;7:645–9.
Lin, Y. C., et al. “Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs.” IEEE Journal of the Electron Devices Society, vol. 7, Jan. 2019, pp. 645–49. Scopus, doi:10.1109/JEDS.2019.2922441.
Lin YC, McGuire F, Noyce S, Williams N, Cheng Z, Andrews J, Franklin AD. Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs. IEEE Journal of the Electron Devices Society. 2019 Jan 1;7:645–649.

Published In

IEEE Journal of the Electron Devices Society

DOI

EISSN

2168-6734

Publication Date

January 1, 2019

Volume

7

Start / End Page

645 / 649

Related Subject Headings

  • 4009 Electronics, sensors and digital hardware
  • 4008 Electrical engineering
  • 1007 Nanotechnology
  • 0906 Electrical and Electronic Engineering