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Exploring the VLSI scalability of stream processors

Publication ,  Conference
Khailany, B; Dally, WJ; Rixner, S; Kapasi, UJ; Owens, JD; Towles, B
Published in: Proceedings - International Symposium on High-Performance Computer Architecture
January 1, 2003

Stream processors are high-performance programmable processors optimized to run media applications. Recent work has shown these processors to be more area-and energy-efficient than conventional programmable architectures. This paper explores the scalability of stream architectures to future VLSI technologies where over a thousand floating-point units on a single chip will be feasible. Two techniques for increasing the number of ALU in a stream processor are presented: intracluster and intercluster scaling. These scaling techniques are shown to be cost-efficient to tens of ALU per cluster and to hundreds of arithmetic clusters. A 640-ALU stream processor with 128 clusters and 5 ALU per cluster is shown to be feasible in 45 nanometer technology, sustaining over 300 GOPS on kernels and providing 15.3× of kernel speedup and 8.0× of application speedup over a 40-ALU stream processor with a 2% degradation in area per ALU and a 7% degradation in energy dissipated per ALU operation.

Duke Scholars

Published In

Proceedings - International Symposium on High-Performance Computer Architecture

DOI

ISSN

1530-0897

Publication Date

January 1, 2003

Volume

12

Start / End Page

153 / 164
 

Citation

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Khailany, B., Dally, W. J., Rixner, S., Kapasi, U. J., Owens, J. D., & Towles, B. (2003). Exploring the VLSI scalability of stream processors. In Proceedings - International Symposium on High-Performance Computer Architecture (Vol. 12, pp. 153–164). https://doi.org/10.1109/HPCA.2003.1183534
Khailany, B., W. J. Dally, S. Rixner, U. J. Kapasi, J. D. Owens, and B. Towles. “Exploring the VLSI scalability of stream processors.” In Proceedings - International Symposium on High-Performance Computer Architecture, 12:153–64, 2003. https://doi.org/10.1109/HPCA.2003.1183534.
Khailany B, Dally WJ, Rixner S, Kapasi UJ, Owens JD, Towles B. Exploring the VLSI scalability of stream processors. In: Proceedings - International Symposium on High-Performance Computer Architecture. 2003. p. 153–64.
Khailany, B., et al. “Exploring the VLSI scalability of stream processors.” Proceedings - International Symposium on High-Performance Computer Architecture, vol. 12, 2003, pp. 153–64. Scopus, doi:10.1109/HPCA.2003.1183534.
Khailany B, Dally WJ, Rixner S, Kapasi UJ, Owens JD, Towles B. Exploring the VLSI scalability of stream processors. Proceedings - International Symposium on High-Performance Computer Architecture. 2003. p. 153–164.

Published In

Proceedings - International Symposium on High-Performance Computer Architecture

DOI

ISSN

1530-0897

Publication Date

January 1, 2003

Volume

12

Start / End Page

153 / 164