Route packets, not wires: On-chip interconnection networks
Publication
, Conference
Dally, WJ; Towles, B
Published in: Proceedings - Design Automation Conference
January 1, 2001
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Duke Scholars
Published In
Proceedings - Design Automation Conference
ISSN
0738-100X
Publication Date
January 1, 2001
Start / End Page
684 / 689
Citation
APA
Chicago
ICMJE
MLA
NLM
Dally, W. J., & Towles, B. (2001). Route packets, not wires: On-chip interconnection networks. In Proceedings - Design Automation Conference (pp. 684–689).
Dally, W. J., and B. Towles. “Route packets, not wires: On-chip interconnection networks.” In Proceedings - Design Automation Conference, 684–89, 2001.
Dally WJ, Towles B. Route packets, not wires: On-chip interconnection networks. In: Proceedings - Design Automation Conference. 2001. p. 684–9.
Dally, W. J., and B. Towles. “Route packets, not wires: On-chip interconnection networks.” Proceedings - Design Automation Conference, 2001, pp. 684–89.
Dally WJ, Towles B. Route packets, not wires: On-chip interconnection networks. Proceedings - Design Automation Conference. 2001. p. 684–689.
Published In
Proceedings - Design Automation Conference
ISSN
0738-100X
Publication Date
January 1, 2001
Start / End Page
684 / 689