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Verification of a practical Hardware security architecture through static information flow analysis

Publication ,  Conference
Ferraiuolo, A; Xu, R; Zhang, D; Myers, AC; Suh, GE
Published in: International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS
April 4, 2017

Hardware-based mechanisms for software isolation are becoming increasingly popular, but implementing these mechanisms correctly has proved difficult, undermining the root of security. This work introduces an effective way to formally verify important properties of such hardware security mechanisms. In our approach, hardware is developed using a lightweight security-typed hardware description language (HDL) that performs static information flow analysis. We show the practicality of our approach by implementing and verifying a simplified but realistic multi-core prototype of the ARM Trust Zone architecture. To make the security-typed HDL expressive enough to verify a realistic processor, we develop new type system features. Our experiments suggest that information flow analysis is efficient, and programmer effort is modest.We also show that information flow constraints are an effective way to detect hardware vulnerabilities, including several found in commercial processors.

Duke Scholars

Published In

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

DOI

Publication Date

April 4, 2017

Volume

Part F127193

Start / End Page

555 / 568

Related Subject Headings

  • Software Engineering
 

Citation

APA
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ICMJE
MLA
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Ferraiuolo, A., Xu, R., Zhang, D., Myers, A. C., & Suh, G. E. (2017). Verification of a practical Hardware security architecture through static information flow analysis. In International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS (Vol. Part F127193, pp. 555–568). https://doi.org/10.1145/3037697.3037739
Ferraiuolo, A., R. Xu, D. Zhang, A. C. Myers, and G. E. Suh. “Verification of a practical Hardware security architecture through static information flow analysis.” In International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS, Part F127193:555–68, 2017. https://doi.org/10.1145/3037697.3037739.
Ferraiuolo A, Xu R, Zhang D, Myers AC, Suh GE. Verification of a practical Hardware security architecture through static information flow analysis. In: International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS. 2017. p. 555–68.
Ferraiuolo, A., et al. “Verification of a practical Hardware security architecture through static information flow analysis.” International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS, vol. Part F127193, 2017, pp. 555–68. Scopus, doi:10.1145/3037697.3037739.
Ferraiuolo A, Xu R, Zhang D, Myers AC, Suh GE. Verification of a practical Hardware security architecture through static information flow analysis. International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS. 2017. p. 555–568.

Published In

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

DOI

Publication Date

April 4, 2017

Volume

Part F127193

Start / End Page

555 / 568

Related Subject Headings

  • Software Engineering