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Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines

Publication ,  Journal Article
Garikapati, S; Nagulu, A; Kadota, I; Essawy, M; Chen, T; Wang, S; Pande, T; Natarajan, AS; Zussman, G; Krishnaswamy, H
Published in: IEEE Journal of Solid-State Circuits
July 1, 2024

The self-interference (SI) channels in full-duplex (FD) radios have large nano-second-scale delay spreads, which poses a significant challenge in designing SI cancelers that can emulate the SI channel over wide bandwidths. Passive implementations of high delay lines have a prohibitively large form factor and loss when implemented on silicon, whereas active implementations suffer from noise and linearity penalties. In this work, we leverage time-interleaved multi-path switched-capacitor (SC) circuits to provide large wideband delays with a small form factor and low power (LP) consumption to implement RF and baseband (BB) cancelers in an FD receiver (RX). We utilize capacitor stacking to obtain passive voltage gain to compensate for the loss of these delay elements, thus permitting an increased number of interleaved paths and, hence, a higher delay. Furthermore, to reduce the RX noise figure (NF) penalty due to injecting the cancellation signal into the receiver, we introduce a novel low-noise trans-impedance amplifier (LNTA) architecture, which injects the cancellation signal into RX and also accomplishes finite impulse response (FIR) filter weighting and summation. The FD receiver is implemented in a standard 65-nm CMOS process and operates from 0.1 to 1 GHz. The RF/BB canceler delay cells have real-/complex-valued weighting with delays ranging from 0 to 7.75 ns/0 to 85 ns while consuming 7.4- and 1.9-mW dc power per tap, respectively. These large tunable delays enable 41-/38-dB integrated SI cancellation for 40-/80-MHz bandwidth over 29-dB isolation provided by a CMOS circulator operating at 0.95 GHz. The canceler handles a transmitter (TX) power of up to +10/+15 dBm in LP/high-power (HP) modes with 0.8-/2.8-dB RX NF degradation.

Duke Scholars

Published In

IEEE Journal of Solid-State Circuits

DOI

EISSN

1558-173X

ISSN

0018-9200

Publication Date

July 1, 2024

Volume

59

Issue

7

Start / End Page

2105 / 2120

Related Subject Headings

  • Electrical & Electronic Engineering
  • 4009 Electronics, sensors and digital hardware
  • 1099 Other Technology
  • 0906 Electrical and Electronic Engineering
  • 0204 Condensed Matter Physics
 

Citation

APA
Chicago
ICMJE
MLA
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Garikapati, S., Nagulu, A., Kadota, I., Essawy, M., Chen, T., Wang, S., … Krishnaswamy, H. (2024). Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines. IEEE Journal of Solid-State Circuits, 59(7), 2105–2120. https://doi.org/10.1109/JSSC.2024.3351615
Garikapati, S., A. Nagulu, I. Kadota, M. Essawy, T. Chen, S. Wang, T. Pande, A. S. Natarajan, G. Zussman, and H. Krishnaswamy. “Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines.” IEEE Journal of Solid-State Circuits 59, no. 7 (July 1, 2024): 2105–20. https://doi.org/10.1109/JSSC.2024.3351615.
Garikapati S, Nagulu A, Kadota I, Essawy M, Chen T, Wang S, et al. Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines. IEEE Journal of Solid-State Circuits. 2024 Jul 1;59(7):2105–20.
Garikapati, S., et al. “Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines.” IEEE Journal of Solid-State Circuits, vol. 59, no. 7, July 2024, pp. 2105–20. Scopus, doi:10.1109/JSSC.2024.3351615.
Garikapati S, Nagulu A, Kadota I, Essawy M, Chen T, Wang S, Pande T, Natarajan AS, Zussman G, Krishnaswamy H. Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines. IEEE Journal of Solid-State Circuits. 2024 Jul 1;59(7):2105–2120.

Published In

IEEE Journal of Solid-State Circuits

DOI

EISSN

1558-173X

ISSN

0018-9200

Publication Date

July 1, 2024

Volume

59

Issue

7

Start / End Page

2105 / 2120

Related Subject Headings

  • Electrical & Electronic Engineering
  • 4009 Electronics, sensors and digital hardware
  • 1099 Other Technology
  • 0906 Electrical and Electronic Engineering
  • 0204 Condensed Matter Physics