CHARACTERIZING the PERFORMANCE of A HIGH-SPEED ADC for the SMA DIGITAL BACKEND

We report on tests of a 5 Gs/s analog-to-digital converter (ADC) used in the new Submillimeter Array (SMA) Digital Backend (DBE). The ADC is e2v EV8AQ160, with 8-bit resolution and 4 interleaved cores, operated in single-channel mode. We measured the frequency response, Signal to Noise and Distortion (SINAD), Spurious Free Dynamic Range (SFDR), Noise Power Ratio and intermodulation distortion over the bandwidth of 2.25 GHz. The performance of this ADC is found to be adequate for our application in the SMA DBE. We describe the procedure of aligning the four cores for adjustments of offset, gain and phase parameters which improve the performance of the ADC, particularly in SINAD and SFDR.

Duke Scholars

Author Ken H Young Pathology