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Compact, precise digital to analog converter arrays in a low cost, low precision short channel CMOS process

Publication ,  Journal Article
Tabler, JA; Poddar, R; Brooke, M
Published in: Midwest Symposium on Circuits and Systems
December 1, 1994

A useful circuit topology for the realization of compact, precise digital to analog converters is presented. The converter architecture uses digital correction to obtain good precision in an inexpensive, non-precision, short channel, digital CMOS process. We present the results of tests performed on the versions of the digital to analog converter test structures fabricated to date. These results are compared with HSPICE Monte Carlo simulations. Large arrays of D to A converters can be fabricated in several inexpensive low precision CMOS processes with thermal stability and trainable linearity characteristics adequate for a wide variety of applications.

Duke Scholars

Published In

Midwest Symposium on Circuits and Systems

Publication Date

December 1, 1994

Volume

2

Start / End Page

1183 / 1186
 

Citation

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MLA
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Tabler, J. A., Poddar, R., & Brooke, M. (1994). Compact, precise digital to analog converter arrays in a low cost, low precision short channel CMOS process. Midwest Symposium on Circuits and Systems, 2, 1183–1186.
Tabler, J. A., R. Poddar, and M. Brooke. “Compact, precise digital to analog converter arrays in a low cost, low precision short channel CMOS process.” Midwest Symposium on Circuits and Systems 2 (December 1, 1994): 1183–86.
Tabler JA, Poddar R, Brooke M. Compact, precise digital to analog converter arrays in a low cost, low precision short channel CMOS process. Midwest Symposium on Circuits and Systems. 1994 Dec 1;2:1183–6.
Tabler, J. A., et al. “Compact, precise digital to analog converter arrays in a low cost, low precision short channel CMOS process.” Midwest Symposium on Circuits and Systems, vol. 2, Dec. 1994, pp. 1183–86.
Tabler JA, Poddar R, Brooke M. Compact, precise digital to analog converter arrays in a low cost, low precision short channel CMOS process. Midwest Symposium on Circuits and Systems. 1994 Dec 1;2:1183–1186.

Published In

Midwest Symposium on Circuits and Systems

Publication Date

December 1, 1994

Volume

2

Start / End Page

1183 / 1186