## LINEAR TIME ALGORITHMS FOR OPTIMAL CMOS LAYOUT.

Publication
, Journal Article

Ravi Nair, ; Bruss, A; Reif, J

December 1, 1985

We consider the problem of efficient CMOS circuit layout which has been formulated into an interesting graph-theoretical problem. A linear-time algorithm is described for optimal layout of a graph when the circuit topology is fixed. A further linear-time algorithm is provided to determine an optimal layout (i. e. , having no diffusion gaps) when such a layout exists in some topology for the circuit. The key to our solution is a finite set of representative graphs which concisely describe topologically distinct paths in planar embedded series-parallel graphs.

### Duke Scholars

## Publication Date

December 1, 1985

## Start / End Page

327 / 338

### Citation

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MLA

NLM

Ravi Nair, ., Bruss, A., & Reif, J. (1985). LINEAR TIME ALGORITHMS FOR OPTIMAL CMOS LAYOUT., 327–338.

Ravi Nair, John H., A. Bruss, and J. Reif. “LINEAR TIME ALGORITHMS FOR OPTIMAL CMOS LAYOUT.,” December 1, 1985, 327–38.

Ravi Nair, Bruss A, Reif J. LINEAR TIME ALGORITHMS FOR OPTIMAL CMOS LAYOUT. 1985 Dec 1;327–38.

Ravi Nair, John H., et al.

*LINEAR TIME ALGORITHMS FOR OPTIMAL CMOS LAYOUT.*Dec. 1985, pp. 327–38.Ravi Nair, Bruss A, Reif J. LINEAR TIME ALGORITHMS FOR OPTIMAL CMOS LAYOUT. 1985 Dec 1;327–338.

## Publication Date

December 1, 1985

## Start / End Page

327 / 338