Simulation and vertification of a chip architecture for electrocardiogram data compression
Publication
, Journal Article
Krakow, WT; Sacks, B; Roy, SC; Batchelor, WE; Bohs, LN; Barr, RC
Published in: Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference
December 1, 1990
The simulation and verification of a VLSI chip for real-time compression of electrocardiogram data is presented. We describe a three-tier simulation process, and tell how this approach assisted in the development of the chip. The verification procedure allowed for consistency checking between all representations of the design. An added benefit of the process was automatic synthesis and layout of a large portion of the chip.
Duke Scholars
Published In
Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference
Publication Date
December 1, 1990
Volume
21
Issue
pt 4
Start / End Page
1677 / 1681
Citation
APA
Chicago
ICMJE
MLA
NLM
Krakow, W. T., Sacks, B., Roy, S. C., Batchelor, W. E., Bohs, L. N., & Barr, R. C. (1990). Simulation and vertification of a chip architecture for electrocardiogram data compression. Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference, 21(pt 4), 1677–1681.
Krakow, W. T., B. Sacks, S. C. Roy, W. E. Batchelor, L. N. Bohs, and R. C. Barr. “Simulation and vertification of a chip architecture for electrocardiogram data compression.” Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference 21, no. pt 4 (December 1, 1990): 1677–81.
Krakow WT, Sacks B, Roy SC, Batchelor WE, Bohs LN, Barr RC. Simulation and vertification of a chip architecture for electrocardiogram data compression. Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference. 1990 Dec 1;21(pt 4):1677–81.
Krakow, W. T., et al. “Simulation and vertification of a chip architecture for electrocardiogram data compression.” Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference, vol. 21, no. pt 4, Dec. 1990, pp. 1677–81.
Krakow WT, Sacks B, Roy SC, Batchelor WE, Bohs LN, Barr RC. Simulation and vertification of a chip architecture for electrocardiogram data compression. Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference. 1990 Dec 1;21(pt 4):1677–1681.
Published In
Modeling and Simulation, Proceedings of the Annual Pittsburgh Conference
Publication Date
December 1, 1990
Volume
21
Issue
pt 4
Start / End Page
1677 / 1681