Enhanced imaging arrays using a sigma delta ADC in Si CMOS for each array pixel
Publication
, Journal Article
Brooke, MA
Published in: LEOS Summer Topical Meeting
January 1, 2000
Recently we have demonstrated a compact current input oversampling modulator for a scalable high frame rate focal plane arrays that enable frame rates over than 100kfps operating in continuous imaging mode. All the circuits including data lines and detectors were laid-out to fit into 125um × 125um space using 0.8um CMOS technology. This compact converter also provides improvement in noise filtering performance over imagers that use capacitance at each pixel to convert detector current to voltage. This technique may allow noisy detectors to be used at high temperatures with good image quality.
Duke Scholars
Published In
LEOS Summer Topical Meeting
ISSN
1099-4742
Publication Date
January 1, 2000
Start / End Page
11 / 12
Citation
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Brooke, M. A. (2000). Enhanced imaging arrays using a sigma delta ADC in Si CMOS for each array pixel. LEOS Summer Topical Meeting, 11–12.
Brooke, M. A. “Enhanced imaging arrays using a sigma delta ADC in Si CMOS for each array pixel.” LEOS Summer Topical Meeting, January 1, 2000, 11–12.
Brooke MA. Enhanced imaging arrays using a sigma delta ADC in Si CMOS for each array pixel. LEOS Summer Topical Meeting. 2000 Jan 1;11–2.
Brooke, M. A. “Enhanced imaging arrays using a sigma delta ADC in Si CMOS for each array pixel.” LEOS Summer Topical Meeting, Jan. 2000, pp. 11–12.
Brooke MA. Enhanced imaging arrays using a sigma delta ADC in Si CMOS for each array pixel. LEOS Summer Topical Meeting. 2000 Jan 1;11–12.
Published In
LEOS Summer Topical Meeting
ISSN
1099-4742
Publication Date
January 1, 2000
Start / End Page
11 / 12