Low conversion ratio VRM design
Publication
, Journal Article
Peterchev, AV; Sanders, SR
Published in: PESC Record - IEEE Annual Power Electronics Specialists Conference
January 1, 2002
This paper discusses the design considerations for low conversion ratio voltage regulation modules (VRM's) for the next generation of microprocessors, focusing on the handling of large, high-slew-rate current transients. A converter topology which deploys an inductive clamp to handle the unloading transients, while operating at a modest switching frequency, low current ripple, and low power dissipation, is discussed. The clamp response is analyzed, and simulation results for a 1 MHz, 100 A, 12-to-1V VRM are presented.
Duke Scholars
Published In
PESC Record - IEEE Annual Power Electronics Specialists Conference
ISSN
0275-9306
Publication Date
January 1, 2002
Volume
4
Start / End Page
1571 / 1575
Citation
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Chicago
ICMJE
MLA
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Peterchev, A. V., & Sanders, S. R. (2002). Low conversion ratio VRM design. PESC Record - IEEE Annual Power Electronics Specialists Conference, 4, 1571–1575.
Peterchev, A. V., and S. R. Sanders. “Low conversion ratio VRM design.” PESC Record - IEEE Annual Power Electronics Specialists Conference 4 (January 1, 2002): 1571–75.
Peterchev AV, Sanders SR. Low conversion ratio VRM design. PESC Record - IEEE Annual Power Electronics Specialists Conference. 2002 Jan 1;4:1571–5.
Peterchev, A. V., and S. R. Sanders. “Low conversion ratio VRM design.” PESC Record - IEEE Annual Power Electronics Specialists Conference, vol. 4, Jan. 2002, pp. 1571–75.
Peterchev AV, Sanders SR. Low conversion ratio VRM design. PESC Record - IEEE Annual Power Electronics Specialists Conference. 2002 Jan 1;4:1571–1575.
Published In
PESC Record - IEEE Annual Power Electronics Specialists Conference
ISSN
0275-9306
Publication Date
January 1, 2002
Volume
4
Start / End Page
1571 / 1575