On the Design and Implementation of a Lossless Data Compression and Decompression Chip

A lossless data compression and decompression (LDCD) algorithm based on the notion of textual substitution has been implemented in silicon using a linear systolic array architecture. This algorithm employs a model where the encoder and decoder each have a finite amount of memory which is referred to as the dictionary. Compression is achieved by finding matches between the dictionary and the input data stream whereby a substitution is made in the data stream by an index referencing the corresponding dictionary entry. The LDCD system is built using 30 application-specific integrated circuits (ASIC’s) each containing 126 identical processing elements (PE’s) which perform both the encoding and decoding function at clock rates up to 20 MHz. © 1993 IEEE

Duke Scholars

Author John H. Reif Computer Science