A parallel architecture for high speed data compression

The authors discuss textual substitution methods. They present a massively parallel architecture for textual substitution that is based on a systolic pipe of 3839 identical processing elements that forms what is essentially an associative memory for strings that can 'learn' new strings on the basis of the text processed thus far. The key to the design of this architecture is the formulation of an inherently top-down serial learning strategy as a bottom-up parallel strategy. A custom VLSI chip for this architecture that is capable of operating at 320-Mb/s has passed all simulations and is being fabricated with 1.2-μm double-metal technology.

Duke Scholars

Author John H. Reif Computer Science