14-bit, 2.2MS/s sigma delta ADCs

Conference Paper

This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a.35μM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation. © 1999 Editions Frontieres.

Duke Authors

Cited Authors

  • Morizio, J; Hoke, M; Kocak, T; Geddie, C; Hughes, C; Perry, J; Madhavapeddi, S; Hood, M; Lynch, G; Kondoh, H; Kumamoto, T; Okuda, T; Noda, H; Ishiwaki, M; Miki, T; Nakaya, M

Published Date

  • December 1, 1999

Published In

Start / End Page

  • 82 - 85

International Standard Serial Number (ISSN)

  • 1930-8833

Citation Source

  • Scopus