14-bit, 2.2MS/s sigma delta ADCs
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, Conference
Morizio, J; Hoke, M; Kocak, T; Geddie, C; Hughes, C; Perry, J; Madhavapeddi, S; Hood, M; Lynch, G; Kondoh, H; Kumamoto, T; Okuda, T; Noda, H ...
Published in: European Solid State Circuits Conference
December 1, 1999
This paper presents the design and test results of a 4th and 6th order, 14-bit, 2.2MS/s sigma-delta ADC. The analog modulator and digital decimator sections were implemented in a.35μM CMOS, double poly, triple level metal 3.3v process. The design objectives for these ADCs was to achieve 85dB SNDR with less than 200mW power dissipation. © 1999 Editions Frontieres.
Duke Scholars
Published In
European Solid State Circuits Conference
ISSN
1930-8833
Publication Date
December 1, 1999
Start / End Page
82 / 85
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Morizio, J., Hoke, M., Kocak, T., Geddie, C., Hughes, C., Perry, J., … Nakaya, M. (1999). 14-bit, 2.2MS/s sigma delta ADCs. In European Solid State Circuits Conference (pp. 82–85).
Morizio, J., M. Hoke, T. Kocak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, et al. “14-bit, 2.2MS/s sigma delta ADCs.” In European Solid State Circuits Conference, 82–85, 1999.
Morizio J, Hoke M, Kocak T, Geddie C, Hughes C, Perry J, et al. 14-bit, 2.2MS/s sigma delta ADCs. In: European Solid State Circuits Conference. 1999. p. 82–5.
Morizio, J., et al. “14-bit, 2.2MS/s sigma delta ADCs.” European Solid State Circuits Conference, 1999, pp. 82–85.
Morizio J, Hoke M, Kocak T, Geddie C, Hughes C, Perry J, Madhavapeddi S, Hood M, Lynch G, Kondoh H, Kumamoto T, Okuda T, Noda H, Ishiwaki M, Miki T, Nakaya M. 14-bit, 2.2MS/s sigma delta ADCs. European Solid State Circuits Conference. 1999. p. 82–85.
Published In
European Solid State Circuits Conference
ISSN
1930-8833
Publication Date
December 1, 1999
Start / End Page
82 / 85