Spin-hall assisted STT-RAM design and discussion
In recent years, Spin-Transfer Torque Random Access Memory (STT-RAM) has attracted significant attentions from both industry and academia due to its attractive attributes such as small cell area and non-volatility. However, long switching time and large programming energy of Magnetic Tunneling Junction (MTJ) continue being major challenges in STT-RAM designs. In order to overcome this problem, a Spin-Hall Effect (SHE) assisted STT-RAM structure (SHE-RAM) has been recently invented. In this work, we investigate two possible SHE-RAM designs from the aspects of two different write access operations, namely, High Density SHE-RAM and Disturbance Free SHE-RAM, respectively. In High Density SHE-RAM, SHE current is shared by the entire bit line. Such a structure removes the SHE control transistor from each SHE-RAM cell and hence, substantially reduces the memory cell area. In Disturbance Free SHE-RAM, one memory cell contains two transistors to remove the disturbance to the unselected bits and eliminate the possible erroneous flipping of the bits.
