Skip to main content

C1C: A configurable, compiler-guided STT-RAM L1 cache

Publication ,  Journal Article
Li, Y; Zhang, Y; Li, H; Chen, Y; Jones, AK
Published in: Transactions on Architecture and Code Optimization
December 1, 2013

Spin-Transfer Torque RAM (STT-RAM), a promising alternative to SRAM for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. Recently, STT-RAM has been proposed for L1 caches by relaxing the data retention time to improve write performance and dynamic energy. However, as the technology scales down from 65nm to 22nm, the performance of the read operation scales poorly due to reduced sense margins and sense amplifier delays. In this article, we leverage a dual-mode STT memory cell to design a configurable L1 cache architecture termed C1C to mitigate read performance barriers with technology scaling. Guided by application access characteristics discovered through novel compiler analyses, the proposed cache adaptively switches between a high performance and a low-power access mode. Our evaluation demonstrates that the proposed cache with compiler guidance outperforms a state-of-the-art STT-RAM cache design by 9% with high dynamic energy efficiency, leading to significant performance/watt improvements over several competing approaches. © 2013 ACM.

Duke Scholars

Published In

Transactions on Architecture and Code Optimization

DOI

EISSN

1544-3973

ISSN

1544-3566

Publication Date

December 1, 2013

Volume

10

Issue

4

Related Subject Headings

  • 4606 Distributed computing and systems software
  • 4009 Electronics, sensors and digital hardware
  • 0906 Electrical and Electronic Engineering
  • 0803 Computer Software
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Li, Y., Zhang, Y., Li, H., Chen, Y., & Jones, A. K. (2013). C1C: A configurable, compiler-guided STT-RAM L1 cache. Transactions on Architecture and Code Optimization, 10(4). https://doi.org/10.1145/2555289.2555308
Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.
Li Y, Zhang Y, Li H, Chen Y, Jones AK. C1C: A configurable, compiler-guided STT-RAM L1 cache. Transactions on Architecture and Code Optimization. 2013 Dec 1;10(4).
Li, Y., et al. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization, vol. 10, no. 4, Dec. 2013. Scopus, doi:10.1145/2555289.2555308.
Li Y, Zhang Y, Li H, Chen Y, Jones AK. C1C: A configurable, compiler-guided STT-RAM L1 cache. Transactions on Architecture and Code Optimization. 2013 Dec 1;10(4).

Published In

Transactions on Architecture and Code Optimization

DOI

EISSN

1544-3973

ISSN

1544-3566

Publication Date

December 1, 2013

Volume

10

Issue

4

Related Subject Headings

  • 4606 Distributed computing and systems software
  • 4009 Electronics, sensors and digital hardware
  • 0906 Electrical and Electronic Engineering
  • 0803 Computer Software