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On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

Publication ,  Journal Article
Chen, Y; Wong, WF; Li, H; Koh, CK; Zhang, Y; Wen, W
Published in: ACM Journal on Emerging Technologies in Computing Systems
October 21, 2013

It has been predicted that a processor's caches could occupy as much as 90% of chip area a few technology nodes from the current ones. In this article, we investigate the use of multilevel spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. We start with examining the access (read and write) scheme for multilevel cell (MLC) STT-RAM from a circuit design perspective, detailing the read and write circuits. Compared to traditional SRAM caches, a multilevel cell (MLC) STT-RAM cache design is denser, fast, and requires less energy. However, a number of critical architecture-level issues remain to be solved before MLC STT-RAM technology can be deployed in processor caches. We shall offer solutions to the issue of bit encoding as well as tackle the write endurance problem. In particular, the latter has been neglected in previous works on STT-RAM caches. We propose a set remapping scheme that can potentially prolong the lifetime of a MLC STT-RAM cache by 80× on average. Furthermore, a method for recovering the performance that may be lost in some applications due to set remapping is proposed. The impacts of process variations of the MLC STT-RAM cell on the robustness of the memory hierarchy is also discussed, together with various enhancement techniques, namely, ECC and design redundancy. © 2013 ACM.

Duke Scholars

Published In

ACM Journal on Emerging Technologies in Computing Systems

DOI

EISSN

1550-4840

ISSN

1550-4832

Publication Date

October 21, 2013

Volume

9

Issue

2

Related Subject Headings

  • Computer Hardware & Architecture
  • 4606 Distributed computing and systems software
  • 1007 Nanotechnology
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Chen, Y., Wong, W. F., Li, H., Koh, C. K., Zhang, Y., & Wen, W. (2013). On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM Journal on Emerging Technologies in Computing Systems, 9(2). https://doi.org/10.1145/2463585.2463592
Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” ACM Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.
Chen Y, Wong WF, Li H, Koh CK, Zhang Y, Wen W. On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM Journal on Emerging Technologies in Computing Systems. 2013 Oct 21;9(2).
Chen, Y., et al. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” ACM Journal on Emerging Technologies in Computing Systems, vol. 9, no. 2, Oct. 2013. Scopus, doi:10.1145/2463585.2463592.
Chen Y, Wong WF, Li H, Koh CK, Zhang Y, Wen W. On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM Journal on Emerging Technologies in Computing Systems. 2013 Oct 21;9(2).

Published In

ACM Journal on Emerging Technologies in Computing Systems

DOI

EISSN

1550-4840

ISSN

1550-4832

Publication Date

October 21, 2013

Volume

9

Issue

2

Related Subject Headings

  • Computer Hardware & Architecture
  • 4606 Distributed computing and systems software
  • 1007 Nanotechnology
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering