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Coordinating prefetching and STT-RAM based last-level cache management for multicore systems

Publication ,  Conference
Mao, M; Li, H; Jones, AK; Chen, Y
Published in: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
May 30, 2013

Data prefetching is a common mechanism to mitigate the bottleneck of off-chip memory bandwidth in modern computing systems. Unfortunately, the side effects of prefetching are an additional burden on off-chip communication and increased cache write operations. With the proposal of spin-transfer torque random access memory (STT-RAM) based last-level caches (LLCs) for their high density and low power consumption, the increase of write pressure to the cache from prefetching coupled with the characteristically long write access compared with traditional SRAM caches exacerbates the performance cost of prefetching schemes. In this work, we propose two orthogonal techniques to reduce the negative performance impact induced by aggressive prefetching on multicore systems employing STT-RAM based LLC. First, basic priority assignment prioritizes the different types of access requests of LLC by their criticality and responds to them based on priority. Second, priority boosting differentiates requests by application and prioritizes the relatively few requests from applications with non-intensive accesses to the LLC, which usually creates the most severe performance degradation in multi-core systems. Combining these two prioritization policies can alleviate the negative effect induced by aggressive prefetching. Our results show that these techniques can achieve an 8.3 average application speedup compared to a baseline, prefetch only design without prioritization. © 2013 ACM.

Duke Scholars

Published In

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

DOI

ISBN

9781450319027

Publication Date

May 30, 2013

Start / End Page

55 / 60
 

Citation

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Mao, M., Li, H., Jones, A. K., & Chen, Y. (2013). Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 55–60). https://doi.org/10.1145/2483028.2483060
Mao, M., H. Li, A. K. Jones, and Y. Chen. “Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.” In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 55–60, 2013. https://doi.org/10.1145/2483028.2483060.
Mao M, Li H, Jones AK, Chen Y. Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2013. p. 55–60.
Mao, M., et al. “Coordinating prefetching and STT-RAM based last-level cache management for multicore systems.” Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2013, pp. 55–60. Scopus, doi:10.1145/2483028.2483060.
Mao M, Li H, Jones AK, Chen Y. Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2013. p. 55–60.

Published In

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

DOI

ISBN

9781450319027

Publication Date

May 30, 2013

Start / End Page

55 / 60