Skip to main content

Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies

Publication ,  Journal Article
Chen, Y; Li, H; Roy, K; Koh, CK
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
December 1, 2009

To minimize the leakage power dissipation of present-day on-chip Decaps, we propose a gated decoupling capacitor (GDecap) technique that deactivates a Decap when it is not needed. The application of the proposed GDecap technique on an eight-way clock-gated clustered pipeline showed that on average, 41.7% Decap leakage power was reduced, with negligible (∼ 0.037) worst-case performance degradation, at the 70-nm technology node. GDecap design incurred an area overhead of around 5.36% when compared with a conventional Decap design. © 2009 IEEE.

Duke Scholars

Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

ISSN

1063-8210

Publication Date

December 1, 2009

Volume

17

Issue

12

Start / End Page

1749 / 1752

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Chen, Y., Li, H., Roy, K., & Koh, C. K. (2009). Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(12), 1749–1752. https://doi.org/10.1109/TVLSI.2008.2007843
Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 12 (December 1, 2009): 1749–52. https://doi.org/10.1109/TVLSI.2008.2007843.
Chen Y, Li H, Roy K, Koh CK. Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009 Dec 1;17(12):1749–52.
Chen, Y., et al. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 12, Dec. 2009, pp. 1749–52. Scopus, doi:10.1109/TVLSI.2008.2007843.
Chen Y, Li H, Roy K, Koh CK. Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009 Dec 1;17(12):1749–1752.

Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

ISSN

1063-8210

Publication Date

December 1, 2009

Volume

17

Issue

12

Start / End Page

1749 / 1752

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing