Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design

In this paper we propose a novel low-power Carry-Select Adder (CSA) design called Cascaded CSA (C2SA). Based on the prediction of the critical path delay of current operation, C²SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C²SA in 180nm Technology show that C²SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) Latency Per Operation (LPO) compared to standard CSA. Copyright 2005 ACM.

Duke Scholars

Author Yiran Chen Electrical and Computer Engineering

Author Hai "Helen" Li Electrical and Computer Engineering