Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies
Publication
, Conference
Chen, Y; Li, H; Roy, K; Koh, CK
Published in: Proceedings of the Custom Integrated Circuits Conference
January 1, 2005
A novel on-chip Decoupling Capacitor (Decap) design - Gated Decoupling Capacitor (GDecap) - is proposed to minimize the leakage power dissipation associated with present-day on-chip decoupling capacitors. Experiments on the application of GDecap in an 8-way clock-gated cluster pipeline show that on average, 41.7% Decap leakage power is improved, with only 0.037% worst-case performance degradation, at 70nm technology node. Around 5.36% area overhead in Decap area is incurred, compared to the conventional Decap deployment. © 2005 IEEE.
Duke Scholars
Published In
Proceedings of the Custom Integrated Circuits Conference
DOI
ISSN
0886-5930
Publication Date
January 1, 2005
Volume
2005
Start / End Page
775 / 778
Citation
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Chen, Y., Li, H., Roy, K., & Koh, C. K. (2005). Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. In Proceedings of the Custom Integrated Circuits Conference (Vol. 2005, pp. 775–778). https://doi.org/10.1109/CICC.2005.1568783
Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Proceedings of the Custom Integrated Circuits Conference, 2005:775–78, 2005. https://doi.org/10.1109/CICC.2005.1568783.
Chen Y, Li H, Roy K, Koh CK. Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. In: Proceedings of the Custom Integrated Circuits Conference. 2005. p. 775–8.
Chen, Y., et al. “Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” Proceedings of the Custom Integrated Circuits Conference, vol. 2005, 2005, pp. 775–78. Scopus, doi:10.1109/CICC.2005.1568783.
Chen Y, Li H, Roy K, Koh CK. Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies. Proceedings of the Custom Integrated Circuits Conference. 2005. p. 775–778.
Published In
Proceedings of the Custom Integrated Circuits Conference
DOI
ISSN
0886-5930
Publication Date
January 1, 2005
Volume
2005
Start / End Page
775 / 778