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Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration

Publication ,  Conference
Zheng, Q; Li, S; Wang, Y; Li, Z; Chen, Y; Li, HL
Published in: Proceedings - IEEE International Symposium on Circuits and Systems
January 1, 2024

Fine-grained sparsity in recent bio-inspired models such as attention-based model could reduce the computation complexity dramatically. However, the unique sparsity pattern challenges the mapping efficiency of the conventional pure analog memristor-based computing architecture, as the conventional one uses a vector-matrix-multiplication primitives. To fill the gap between the memristor-based architecture and the sparse processing, in this paper, we would like to present our recent progress by using a hybrid digital/analog memristor-based computing architecture to improve the mapping efficiency. Our evaluation result shows that, over previous pure analog memristor-based architecture, our design could deliver up to 8.32× performance improvement and 3.4× energy efficiency improvement on a range of vision and language tasks for the recent attention-based bio-inspired model.

Duke Scholars

Published In

Proceedings - IEEE International Symposium on Circuits and Systems

DOI

ISSN

0271-4310

Publication Date

January 1, 2024
 

Citation

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Zheng, Q., Li, S., Wang, Y., Li, Z., Chen, Y., & Li, H. L. (2024). Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration. In Proceedings - IEEE International Symposium on Circuits and Systems. https://doi.org/10.1109/ISCAS58744.2024.10558703
Zheng, Q., S. Li, Y. Wang, Z. Li, Y. Chen, and H. L. Li. “Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration.” In Proceedings - IEEE International Symposium on Circuits and Systems, 2024. https://doi.org/10.1109/ISCAS58744.2024.10558703.
Zheng Q, Li S, Wang Y, Li Z, Chen Y, Li HL. Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration. In: Proceedings - IEEE International Symposium on Circuits and Systems. 2024.
Zheng, Q., et al. “Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration.” Proceedings - IEEE International Symposium on Circuits and Systems, 2024. Scopus, doi:10.1109/ISCAS58744.2024.10558703.
Zheng Q, Li S, Wang Y, Li Z, Chen Y, Li HL. Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration. Proceedings - IEEE International Symposium on Circuits and Systems. 2024.

Published In

Proceedings - IEEE International Symposium on Circuits and Systems

DOI

ISSN

0271-4310

Publication Date

January 1, 2024