Circuits to Systems: Codesigning Efficient AI Hardware
Publication
, Journal Article
Chen, Y; Guo, C; He, Y; Ma, M; Molom-Ochir, T; Ramos, N; Shan, H; Wei, C; Li, H
Published in: IEEE Design and Test
January 1, 2025
The authors explore the intertwined progress of circuit innovation and system architecture that has propelled AI development—from early neuro-morphic circuits to today’s memory-centric accelerators. They review milestones such as processing-in-memory, GPUs, and systolic arrays and address emerging challenges from large language models.
Duke Scholars
Published In
IEEE Design and Test
DOI
EISSN
2168-2364
ISSN
2168-2356
Publication Date
January 1, 2025
Volume
42
Issue
6
Start / End Page
54 / 62
Citation
APA
Chicago
ICMJE
MLA
NLM
Chen, Y., Guo, C., He, Y., Ma, M., Molom-Ochir, T., Ramos, N., … Li, H. (2025). Circuits to Systems: Codesigning Efficient AI Hardware. IEEE Design and Test, 42(6), 54–62. https://doi.org/10.1109/MDAT.2025.3600328
Chen, Y., C. Guo, Y. He, M. Ma, T. Molom-Ochir, N. Ramos, H. Shan, C. Wei, and H. Li. “Circuits to Systems: Codesigning Efficient AI Hardware.” IEEE Design and Test 42, no. 6 (January 1, 2025): 54–62. https://doi.org/10.1109/MDAT.2025.3600328.
Chen Y, Guo C, He Y, Ma M, Molom-Ochir T, Ramos N, et al. Circuits to Systems: Codesigning Efficient AI Hardware. IEEE Design and Test. 2025 Jan 1;42(6):54–62.
Chen, Y., et al. “Circuits to Systems: Codesigning Efficient AI Hardware.” IEEE Design and Test, vol. 42, no. 6, Jan. 2025, pp. 54–62. Scopus, doi:10.1109/MDAT.2025.3600328.
Chen Y, Guo C, He Y, Ma M, Molom-Ochir T, Ramos N, Shan H, Wei C, Li H. Circuits to Systems: Codesigning Efficient AI Hardware. IEEE Design and Test. 2025 Jan 1;42(6):54–62.
Published In
IEEE Design and Test
DOI
EISSN
2168-2364
ISSN
2168-2356
Publication Date
January 1, 2025
Volume
42
Issue
6
Start / End Page
54 / 62