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NANA: A nano-scale active network architecture

Journal articles  - Review
Patwardhan, JP; Dwyer, C; Lebeck, AR; Sorin, DJ
Published in: ACM Journal on Emerging Technologies in Computing Systems
January 1, 2006
Published version (DOI)

This article explores the architectural challenges introduced by emerging bottom-up fabrication of nanoelectronic circuits. The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit (node). Three characteristics of this technology that significantly impact architecture are (1) limited node size, (2) random node interconnection, and (3) high defect rates. We present and evaluate an accumulator-based active network architecture that is compatible with any technology that presents these three challenges. This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly. © 2006 ACM.

Duke Scholars

Daniel J. Sorin
Author Daniel J. Sorin Pierre R. Lamond Department of Electrical and Computer Engin ...
Alvin R. Lebeck
Author Alvin R. Lebeck Computer Science
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Published In

ACM Journal on Emerging Technologies in Computing Systems

DOI

10.1145/1126257.1126258

ISSN

1550-4832

Publication Date

January 1, 2006

Volume

2

Issue

1

Start / End Page

1 / 30

Related Subject Headings

  • Computer Hardware & Architecture
  • 4606 Distributed computing and systems software
 

Citation

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MLA
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Patwardhan, J. P., Dwyer, C., Lebeck, A. R., & Sorin, D. J. (2006). NANA: A nano-scale active network architecture. ACM Journal on Emerging Technologies in Computing Systems, 2(1), 1–30. https://doi.org/10.1145/1126257.1126258
Patwardhan, J. P., C. Dwyer, A. R. Lebeck, and D. J. Sorin. “NANA: A nano-scale active network architecture.” ACM Journal on Emerging Technologies in Computing Systems 2, no. 1 (January 1, 2006): 1–30. https://doi.org/10.1145/1126257.1126258.
Patwardhan JP, Dwyer C, Lebeck AR, Sorin DJ. NANA: A nano-scale active network architecture. ACM Journal on Emerging Technologies in Computing Systems. 2006 Jan 1;2(1):1–30.
Patwardhan, J. P., et al. “NANA: A nano-scale active network architecture.” ACM Journal on Emerging Technologies in Computing Systems, vol. 2, no. 1, Jan. 2006, pp. 1–30. Scopus, doi:10.1145/1126257.1126258.
Patwardhan JP, Dwyer C, Lebeck AR, Sorin DJ. NANA: A nano-scale active network architecture. ACM Journal on Emerging Technologies in Computing Systems. 2006 Jan 1;2(1):1–30.

Published In

ACM Journal on Emerging Technologies in Computing Systems

DOI

10.1145/1126257.1126258

ISSN

1550-4832

Publication Date

January 1, 2006

Volume

2

Issue

1

Start / End Page

1 / 30

Related Subject Headings

  • Computer Hardware & Architecture
  • 4606 Distributed computing and systems software