Address translation aware memory consistency
Publication
, Journal Article
Romanescu, B; Lebeck, A; Sorin, DJ
Published in: IEEE Micro
January 1, 2011
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware memory consistency models addresses this need. © 2011 IEEE.
Duke Scholars
Published In
IEEE Micro
DOI
ISSN
0272-1732
Publication Date
January 1, 2011
Volume
31
Issue
1
Start / End Page
109 / 118
Related Subject Headings
- Computer Hardware & Architecture
- 4606 Distributed computing and systems software
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering
Citation
APA
Chicago
ICMJE
MLA
NLM
Romanescu, B., Lebeck, A., & Sorin, D. J. (2011). Address translation aware memory consistency. IEEE Micro, 31(1), 109–118. https://doi.org/10.1109/MM.2010.99
Romanescu, B., A. Lebeck, and D. J. Sorin. “Address translation aware memory consistency.” IEEE Micro 31, no. 1 (January 1, 2011): 109–18. https://doi.org/10.1109/MM.2010.99.
Romanescu B, Lebeck A, Sorin DJ. Address translation aware memory consistency. IEEE Micro. 2011 Jan 1;31(1):109–18.
Romanescu, B., et al. “Address translation aware memory consistency.” IEEE Micro, vol. 31, no. 1, Jan. 2011, pp. 109–18. Scopus, doi:10.1109/MM.2010.99.
Romanescu B, Lebeck A, Sorin DJ. Address translation aware memory consistency. IEEE Micro. 2011 Jan 1;31(1):109–118.
Published In
IEEE Micro
DOI
ISSN
0272-1732
Publication Date
January 1, 2011
Volume
31
Issue
1
Start / End Page
109 / 118
Related Subject Headings
- Computer Hardware & Architecture
- 4606 Distributed computing and systems software
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering