FPGA design of arbitrary down-sampler
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Jorgovanovic, M; Pajic, M; Kvascev, G; Popovic, J
Published in: Microelectronics, 2008. MIEL 2008. 26th International Conference on
May 2008
This paper describes the FPGA design of an arbitrary down-sampler. The arbitrary down-sampler performs decimation of the input signal, adjusting its sample rate to the requirements on the system output. The solution presented in this paper introduces the down-sampler that can adjust its resampling ratio to whatever output frequency if it is in the range within estimation provided. Resource utilization for an FPGA implementation on Xilinx Virtex4 chip is also summarized.
Duke Scholars
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Microelectronics, 2008. MIEL 2008. 26th International Conference on
DOI
Publication Date
May 2008
Start / End Page
391 / 394
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Jorgovanovic, M., Pajic, M., Kvascev, G., & Popovic, J. (2008). FPGA design of arbitrary down-sampler. In Microelectronics, 2008. MIEL 2008. 26th International Conference on (pp. 391–394). https://doi.org/10.1109/ICMEL.2008.4559303
Jorgovanovic, M., M. Pajic, G. Kvascev, and J. Popovic. “FPGA design of arbitrary down-sampler.” In Microelectronics, 2008. MIEL 2008. 26th International Conference On, 391–94, 2008. https://doi.org/10.1109/ICMEL.2008.4559303.
Jorgovanovic M, Pajic M, Kvascev G, Popovic J. FPGA design of arbitrary down-sampler. In: Microelectronics, 2008 MIEL 2008 26th International Conference on. 2008. p. 391–4.
Jorgovanovic, M., et al. “FPGA design of arbitrary down-sampler.” Microelectronics, 2008. MIEL 2008. 26th International Conference On, 2008, pp. 391–94. Manual, doi:10.1109/ICMEL.2008.4559303.
Jorgovanovic M, Pajic M, Kvascev G, Popovic J. FPGA design of arbitrary down-sampler. Microelectronics, 2008 MIEL 2008 26th International Conference on. 2008. p. 391–394.
Published In
Microelectronics, 2008. MIEL 2008. 26th International Conference on
DOI
Publication Date
May 2008
Start / End Page
391 / 394