Decoupling loads for nano-instruction set computers
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- Academic article
Hilton, AD; Lee, BC; Huang, Z
Published in: Proceedings of The 43rd International Symposium on Computer Architecture
We propose an ISA extension that decouples the data access and register write operations in a load instruction. We describe system and hardware support for decoupled loads. Furthermore, we show how compilers can generate better static instruction schedules by hoisting a decoupled load’s data access above may-alias stores and branches. We find that decoupled loads improve performance with geometric mean speedups of 8.4%.
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Proceedings of The 43rd International Symposium on Computer Architecture
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Hilton, A. D., Lee, B. C., & Huang, Z. (n.d.). Decoupling loads for nano-instruction set computers. Proceedings of The 43rd International Symposium on Computer Architecture.
Hilton, A. D., B. C. Lee, and Z. Huang. “Decoupling loads for nano-instruction set computers.” Proceedings of The 43rd International Symposium on Computer Architecture, n.d.
Hilton AD, Lee BC, Huang Z. Decoupling loads for nano-instruction set computers. Proceedings of The 43rd International Symposium on Computer Architecture.
Hilton, A. D., et al. “Decoupling loads for nano-instruction set computers.” Proceedings of The 43rd International Symposium on Computer Architecture.
Hilton AD, Lee BC, Huang Z. Decoupling loads for nano-instruction set computers. Proceedings of The 43rd International Symposium on Computer Architecture.
Published In
Proceedings of The 43rd International Symposium on Computer Architecture
Article type
Other