Modeling Physical Limitations on Junction Scaling for CMOS
Publication
, Journal Article
Fair, RB; Wortman, JJ; Masnari, NA; Mike Tischler, JL
Published in: IEEE Transactions on Electron Devices
January 1, 1984
Accurate calculations of diffusion and ion-implantition processes in silicon require the utilization of complex steady-state physical models that include the effects of both vacancies and self-intersti tials. A new one-dimensional computer program, PROSIM II, has been developed for use in experimental junction formation studies that impact on advanced MOS technologies. PROSIM II has been used to study the scaling limits of counter-doped junctions for CMOS using both conventional furnace annealing and rapid thermal annealing processes. It is found that double implants of boron and arsenic can be used to produce a minimum 3000-A-deep junction and still satisfy sheet resistance requirements for a I-μm process. © 1984 IEEE
Duke Scholars
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Published In
IEEE Transactions on Electron Devices
DOI
EISSN
1557-9646
ISSN
0018-9383
Publication Date
January 1, 1984
Volume
31
Issue
9
Start / End Page
1180 / 1185
Related Subject Headings
- Applied Physics
- 4009 Electronics, sensors and digital hardware
- 0906 Electrical and Electronic Engineering
Citation
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Fair, R. B., Wortman, J. J., Masnari, N. A., & Mike Tischler, J. L. (1984). Modeling Physical Limitations on Junction Scaling for CMOS. IEEE Transactions on Electron Devices, 31(9), 1180–1185. https://doi.org/10.1109/T-ED.1984.21685
Fair, R. B., J. J. Wortman, N. A. Masnari, and J. L. Mike Tischler. “Modeling Physical Limitations on Junction Scaling for CMOS.” IEEE Transactions on Electron Devices 31, no. 9 (January 1, 1984): 1180–85. https://doi.org/10.1109/T-ED.1984.21685.
Fair RB, Wortman JJ, Masnari NA, Mike Tischler JL. Modeling Physical Limitations on Junction Scaling for CMOS. IEEE Transactions on Electron Devices. 1984 Jan 1;31(9):1180–5.
Fair, R. B., et al. “Modeling Physical Limitations on Junction Scaling for CMOS.” IEEE Transactions on Electron Devices, vol. 31, no. 9, Jan. 1984, pp. 1180–85. Scopus, doi:10.1109/T-ED.1984.21685.
Fair RB, Wortman JJ, Masnari NA, Mike Tischler JL. Modeling Physical Limitations on Junction Scaling for CMOS. IEEE Transactions on Electron Devices. 1984 Jan 1;31(9):1180–1185.
Published In
IEEE Transactions on Electron Devices
DOI
EISSN
1557-9646
ISSN
0018-9383
Publication Date
January 1, 1984
Volume
31
Issue
9
Start / End Page
1180 / 1185
Related Subject Headings
- Applied Physics
- 4009 Electronics, sensors and digital hardware
- 0906 Electrical and Electronic Engineering