Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration
Publication
, Conference
Wang, J; Roy, P; Wong, W-F; Bi, X; Li, HH
Published in: 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
January 1, 2014
Duke Scholars
Published In
2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
ISSN
1063-6404
Publication Date
January 1, 2014
Start / End Page
126 / 131
Location
Seoul, SOUTH KOREA
Publisher
IEEE
Conference Name
32nd IEEE International Conference on Computer Design (ICCD)
Citation
APA
Chicago
ICMJE
MLA
NLM
Wang, J., Roy, P., Wong, W.-F., Bi, X., & Li, H. H. (2014). Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration. In 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD) (pp. 126–131). Seoul, SOUTH KOREA: IEEE.
Wang, Jianxing, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Helen Li. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” In 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 126–31. IEEE, 2014.
Wang J, Roy P, Wong W-F, Bi X, Li HH. Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration. In: 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD). IEEE; 2014. p. 126–31.
Wang, Jianxing, et al. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), IEEE, 2014, pp. 126–31.
Wang J, Roy P, Wong W-F, Bi X, Li HH. Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration. 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD). IEEE; 2014. p. 126–131.
Published In
2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)
ISSN
1063-6404
Publication Date
January 1, 2014
Start / End Page
126 / 131
Location
Seoul, SOUTH KOREA
Publisher
IEEE
Conference Name
32nd IEEE International Conference on Computer Design (ICCD)