Identifying wafer-level systematic failure patterns via unsupervised learning
In this paper, we propose a novel methodology for detecting systematic failure patterns at the wafer level for yield learning. Our proposed methodology takes the binary testing results (i.e., pass or fail) of all dies over multiple wafers, cluster these wafers according to their spatial signatures of failures, and eventually identify the underlying systematic failure patterns. Several data processing techniques, including singular value decomposition, hierarchical clustering, etc., are adopted to make the proposed methodology robust to random failures. In addition, a Pseudo-Boolean satisfiability solver is used to extract a minimal set of systematic failure patterns that explain all wafer-level spatial signatures. These patterns help process engineers identify the root causes of failures and accelerate yield learning. The efficacy of our proposed approach is demonstrated by one synthetic data set and one industrial data set.
Duke Scholars
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Related Subject Headings
- Computer Hardware & Architecture
- 4607 Graphics, augmented reality and games
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering
Citation
Published In
DOI
ISSN
Publication Date
Volume
Issue
Start / End Page
Related Subject Headings
- Computer Hardware & Architecture
- 4607 Graphics, augmented reality and games
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering