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Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)

Publication ,  Journal Article
Xu, W; Sun, H; Wang, X; Chen, Y; Zhang, T
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
March 1, 2011

Because of its high storage density with superior scalability, low integration cost and reasonably high access speed, spin-torque transfer random access memory (STT RAM) appears to have a promising potential to replace SRAM as last-level on-chip cache (e.g., L2 or L3 cache) for microprocessors. Due to unique operational characteristics of its storage device magnetic tunneling junction (MTJ), STT RAM is inherently subject to a write latency versus read latency tradeoff that is determined by the memory cell size. This paper first quantitatively studies how different memory cell sizing may impact the overall computing system performance, and shows that different computing workloads may have conflicting expectations on memory cell sizing. Leveraging MTJ device switching characteristics, we further propose an STT RAM architecture design method that can make STT RAM cache with relatively small memory cell size perform well over a wide spectrum of computing benchmarks. This has been well demonstrated using CACTI-based memory modeling and computing system performance simulations using SimpleScalar. Moreover, we show that this design method can also reduce STT RAM cache energy consumption by up to 30% over a variety of benchmarks. © 2006 IEEE.

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Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

ISSN

1063-8210

Publication Date

March 1, 2011

Volume

19

Issue

3

Start / End Page

483 / 493

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing
 

Citation

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Xu, W., Sun, H., Wang, X., Chen, Y., & Zhang, T. (2011). Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM). IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(3), 483–493. https://doi.org/10.1109/TVLSI.2009.2035509
Xu, W., H. Sun, X. Wang, Y. Chen, and T. Zhang. “Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM).” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 3 (March 1, 2011): 483–93. https://doi.org/10.1109/TVLSI.2009.2035509.
Xu W, Sun H, Wang X, Chen Y, Zhang T. Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2011 Mar 1;19(3):483–93.
Xu, W., et al. “Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM).” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, Mar. 2011, pp. 483–93. Scopus, doi:10.1109/TVLSI.2009.2035509.
Xu W, Sun H, Wang X, Chen Y, Zhang T. Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM). IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2011 Mar 1;19(3):483–493.

Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

ISSN

1063-8210

Publication Date

March 1, 2011

Volume

19

Issue

3

Start / End Page

483 / 493

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing