Scholars@Duke

An FPGA-Based Hardware Accelerator for Traffic Sign Detection

Publication ,  Journal Article
Shi, W; Li, X; Yu, Z; Overett, G
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
April 1, 2017
Published version (DOI)

Traffic sign detection plays an important role in a number of practical applications, such as intelligent driver assistance and roadway inventory management. In order to process the large amount of data from either real-time videos or large off-line databases, a high-throughput traffic sign detection system is required. In this paper, we propose an FPGA-based hardware accelerator for traffic sign detection based on cascade classifiers. To maximize the throughput and power efficiency, we propose several novel ideas, including: 1) rearranged numerical operations; 2) shared image storage; 3) adaptive workload distribution; and 4) fast image block integration. The proposed design is evaluated on a Xilinx ZC706 board. When processing high-definition (1080p) video, it achieves the throughput of 126 frames/s and the energy efficiency of 0.041 J/frame.

Duke Scholars

Xin Li
Author Xin Li Electrical and Computer Engineering

Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

10.1109/TVLSI.2016.2631428

ISSN

1063-8210

Publication Date

April 1, 2017

Volume

25

Issue

4

Start / End Page

1362 / 1372

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing
 

Citation

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ICMJE
MLA
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Shi, W., Li, X., Yu, Z., & Overett, G. (2017). An FPGA-Based Hardware Accelerator for Traffic Sign Detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4), 1362–1372. https://doi.org/10.1109/TVLSI.2016.2631428
Shi, W., X. Li, Z. Yu, and G. Overett. “An FPGA-Based Hardware Accelerator for Traffic Sign Detection.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (April 1, 2017): 1362–72. https://doi.org/10.1109/TVLSI.2016.2631428.
Shi W, Li X, Yu Z, Overett G. An FPGA-Based Hardware Accelerator for Traffic Sign Detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 Apr 1;25(4):1362–72.
Shi, W., et al. “An FPGA-Based Hardware Accelerator for Traffic Sign Detection.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 4, Apr. 2017, pp. 1362–72. Scopus, doi:10.1109/TVLSI.2016.2631428.
Shi W, Li X, Yu Z, Overett G. An FPGA-Based Hardware Accelerator for Traffic Sign Detection. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2017 Apr 1;25(4):1362–1372.

Published In

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

DOI

10.1109/TVLSI.2016.2631428

ISSN

1063-8210

Publication Date

April 1, 2017

Volume

25

Issue

4

Start / End Page

1362 / 1372

Related Subject Headings

  • Computer Hardware & Architecture
  • 4009 Electronics, sensors and digital hardware
  • 1006 Computer Hardware
  • 0906 Electrical and Electronic Engineering
  • 0805 Distributed Computing