Active on-die suppression of power supply noise
Publication
, Conference
Keskin, G; Li, X; Pileggi, L
Published in: Proceedings of the Custom Integrated Circuits Conference
December 1, 2006
An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that comparable overshoot/undershoot and ringing control via onchip decoupling would require significantly more area and power due to leakage, particularly at 90nm and below. © 2006 IEEE.
Duke Scholars
Published In
Proceedings of the Custom Integrated Circuits Conference
DOI
ISSN
0886-5930
Publication Date
December 1, 2006
Start / End Page
813 / 816
Citation
APA
Chicago
ICMJE
MLA
NLM
Keskin, G., Li, X., & Pileggi, L. (2006). Active on-die suppression of power supply noise. In Proceedings of the Custom Integrated Circuits Conference (pp. 813–816). https://doi.org/10.1109/CICC.2006.321012
Keskin, G., X. Li, and L. Pileggi. “Active on-die suppression of power supply noise.” In Proceedings of the Custom Integrated Circuits Conference, 813–16, 2006. https://doi.org/10.1109/CICC.2006.321012.
Keskin G, Li X, Pileggi L. Active on-die suppression of power supply noise. In: Proceedings of the Custom Integrated Circuits Conference. 2006. p. 813–6.
Keskin, G., et al. “Active on-die suppression of power supply noise.” Proceedings of the Custom Integrated Circuits Conference, 2006, pp. 813–16. Scopus, doi:10.1109/CICC.2006.321012.
Keskin G, Li X, Pileggi L. Active on-die suppression of power supply noise. Proceedings of the Custom Integrated Circuits Conference. 2006. p. 813–816.
Published In
Proceedings of the Custom Integrated Circuits Conference
DOI
ISSN
0886-5930
Publication Date
December 1, 2006
Start / End Page
813 / 816