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Efficient statistical analysis of read timing failures in sram circuits

Publication ,  Conference
Yaldiz, S; Arslan, U; Li, X; Pileggi, L
Published in: Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
July 8, 2009

A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is impractical to analyze statistically via transistor-level Monte Carlo simulations. The accurate bounding of read timing failures using this methodology is validated with silicon measurements from a 64kb SRAM testchip in 90nm CMOS. We demonstrate the efficacy of this methodology for earlystage design exploration to specify redundancy, required sense amp offset, and other circuit choices as a function of memory size. © 2009 IEEE.

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Published In

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

DOI

Publication Date

July 8, 2009

Start / End Page

617 / 621
 

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Yaldiz, S., Arslan, U., Li, X., & Pileggi, L. (2009). Efficient statistical analysis of read timing failures in sram circuits. In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 (pp. 617–621). https://doi.org/10.1109/ISQED.2009.4810365
Yaldiz, S., U. Arslan, X. Li, and L. Pileggi. “Efficient statistical analysis of read timing failures in sram circuits.” In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009, 617–21, 2009. https://doi.org/10.1109/ISQED.2009.4810365.
Yaldiz S, Arslan U, Li X, Pileggi L. Efficient statistical analysis of read timing failures in sram circuits. In: Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 617–21.
Yaldiz, S., et al. “Efficient statistical analysis of read timing failures in sram circuits.” Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009, 2009, pp. 617–21. Scopus, doi:10.1109/ISQED.2009.4810365.
Yaldiz S, Arslan U, Li X, Pileggi L. Efficient statistical analysis of read timing failures in sram circuits. Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 617–621.

Published In

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

DOI

Publication Date

July 8, 2009

Start / End Page

617 / 621