Skip to main content

A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform

Publication ,  Conference
Fu, W; Yang, J; Dai, P; Chen, Y; Zhao, W
Published in: Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018
December 1, 2018

Region proposal is critical for object detection while it usually poses a bottleneck in improving the computation efficiency on traditional control-flow architectures. We have observed region proposal tasks are potentially suitable for performing pipelined parallelism by exploiting dataflow driven acceleration. In this paper, a scalable pipelined dataflow accelerator is proposed for efficient region proposals on FPGA platform. The accelerator processes image data by a streaming manner with three sequential stages: resizing, kernel computing and sorting. First, Ping-Pong cache strategy is adopted for rotation loading in resize module to guarantee continuous output streaming. Then, a multiple pipelines architecture with tiered memory is utilized in kernel computing module to complete the main computation tasks. Finally, a bubble-pushing heap sort method is exploited in sorting module to find the top-k largest candidates efficiently. Our design is implemented with high level synthesis on FPGA platforms, and experimental re-sults on VOC2007 datasets show that it could achieve about 3.67X speedups than traditional desktop CPU platform and >250X energy efficiency improvement than embedded ARM platform.

Duke Scholars

Published In

Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018

DOI

Publication Date

December 1, 2018

Start / End Page

349 / 352
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Fu, W., Yang, J., Dai, P., Chen, Y., & Zhao, W. (2018). A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. In Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018 (pp. 349–352). https://doi.org/10.1109/FPT.2018.00070
Fu, W., J. Yang, P. Dai, Y. Chen, and W. Zhao. “A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.” In Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018, 349–52, 2018. https://doi.org/10.1109/FPT.2018.00070.
Fu W, Yang J, Dai P, Chen Y, Zhao W. A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. In: Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. 2018. p. 349–52.
Fu, W., et al. “A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.” Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018, 2018, pp. 349–52. Scopus, doi:10.1109/FPT.2018.00070.
Fu W, Yang J, Dai P, Chen Y, Zhao W. A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018. 2018. p. 349–352.

Published In

Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018

DOI

Publication Date

December 1, 2018

Start / End Page

349 / 352