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Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors

Publication ,  Conference
Chen, Y; Roy, K; Koh, CK
Published in: Proceedings of the International Symposium on Low Power Electronics and Design
January 1, 2003

We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors. The proposed approach combines dynamic selection of functional units on-the-fly, dynamic issue width scaling and physical planning with soft module, to balance the current demand across layout. Experimental results show that the proposed approach could reduce the peak noise by 6.54% and consequently, the decoupling capacitance requirement by 21.8%. The degradation in IPC (Instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18μm technology.

Duke Scholars

Published In

Proceedings of the International Symposium on Low Power Electronics and Design

DOI

ISSN

1533-4678

Publication Date

January 1, 2003

Start / End Page

229 / 234
 

Citation

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Chen, Y., Roy, K., & Koh, C. K. (2003). Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 229–234). https://doi.org/10.1145/871506.871563
Chen, Y., K. Roy, and C. K. Koh. “Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors.” In Proceedings of the International Symposium on Low Power Electronics and Design, 229–34, 2003. https://doi.org/10.1145/871506.871563.
Chen Y, Roy K, Koh CK. Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors. In: Proceedings of the International Symposium on Low Power Electronics and Design. 2003. p. 229–34.
Chen, Y., et al. “Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors.” Proceedings of the International Symposium on Low Power Electronics and Design, 2003, pp. 229–34. Scopus, doi:10.1145/871506.871563.
Chen Y, Roy K, Koh CK. Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors. Proceedings of the International Symposium on Low Power Electronics and Design. 2003. p. 229–234.

Published In

Proceedings of the International Symposium on Low Power Electronics and Design

DOI

ISSN

1533-4678

Publication Date

January 1, 2003

Start / End Page

229 / 234