## Fast Statistical Analysis of Rare Circuit Failure Events

Accurately estimating the rare failure rates for nanoscale memory circuits is a challenging task, especially when the variation space is high-dimensional. In this chapter, we summarize two novel techniques to address this technical challenge. First, we describe a subset simulation (SUS) technique to estimate the rare failure rates for continuous performance metrics. The key idea of SUS is to express the rare failure probability of a given circuit as the product of several large conditional probabilities by introducing a number of intermediate failure events. These conditional probabilities can be efficiently estimated with a set of Markov chain Monte Carlo samples generated by a modified Metropolis algorithm. Second, to efficiently estimate the rare failure rates for discrete performance metrics, scaled-sigma sampling (SSS) can be used. SSS aims to generate random samples from a distorted probability distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of “soft maximum”. Our experimental results of several nanoscale circuit examples demonstrate that SUS and SSS achieve significantly improved accuracy over other traditional techniques when the dimensionality of the variation space is more than a few hundred.

### Duke Scholars

### Citation

*Machine Learning in VLSI Computer-Aided Design*(pp. 349–373). https://doi.org/10.1007/978-3-030-04666-8_12

*Machine Learning in VLSI Computer-Aided Design*, 349–73, 2019. https://doi.org/10.1007/978-3-030-04666-8_12.

*Machine Learning in VLSI Computer-Aided Design*, 2019, pp. 349–73.

*Scopus*, doi:10.1007/978-3-030-04666-8_12.