Skip to main content
release_alert
Welcome to the new Scholars 3.0! Read about new features and let us know what you think.
cancel
Journal cover image

Barrier engineering for double layer CVD graphene tunnel FETs

Publication ,  Journal Article
Roy, T; Hesabi, ZR; Joiner, CA; Fujimoto, A; Vogel, EM
Published in: Microelectronic Engineering
May 1, 2013

Atomic layer deposited high-k dielectrics with sputtered TiOx as the seeding layer have been explored for double layer graphene tunnel transistors. The subthreshold swing of these transistors is <100 mV/decade. Temperature-dependent measurements indicate defect-mediated tunneling through these dielectrics. However, the current symmetry can still be altered by engineering the tunnel barriers. © 2013 Elsevier Ltd. All rights reserved.

Duke Scholars

Published In

Microelectronic Engineering

DOI

ISSN

0167-9317

Publication Date

May 1, 2013

Volume

109

Start / End Page

117 / 119

Related Subject Headings

  • Applied Physics
  • 0906 Electrical and Electronic Engineering
  • 0299 Other Physical Sciences
  • 0204 Condensed Matter Physics
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Roy, T., Hesabi, Z. R., Joiner, C. A., Fujimoto, A., & Vogel, E. M. (2013). Barrier engineering for double layer CVD graphene tunnel FETs. Microelectronic Engineering, 109, 117–119. https://doi.org/10.1016/j.mee.2013.02.090
Roy, T., Z. R. Hesabi, C. A. Joiner, A. Fujimoto, and E. M. Vogel. “Barrier engineering for double layer CVD graphene tunnel FETs.” Microelectronic Engineering 109 (May 1, 2013): 117–19. https://doi.org/10.1016/j.mee.2013.02.090.
Roy T, Hesabi ZR, Joiner CA, Fujimoto A, Vogel EM. Barrier engineering for double layer CVD graphene tunnel FETs. Microelectronic Engineering. 2013 May 1;109:117–9.
Roy, T., et al. “Barrier engineering for double layer CVD graphene tunnel FETs.” Microelectronic Engineering, vol. 109, May 2013, pp. 117–19. Scopus, doi:10.1016/j.mee.2013.02.090.
Roy T, Hesabi ZR, Joiner CA, Fujimoto A, Vogel EM. Barrier engineering for double layer CVD graphene tunnel FETs. Microelectronic Engineering. 2013 May 1;109:117–119.
Journal cover image

Published In

Microelectronic Engineering

DOI

ISSN

0167-9317

Publication Date

May 1, 2013

Volume

109

Start / End Page

117 / 119

Related Subject Headings

  • Applied Physics
  • 0906 Electrical and Electronic Engineering
  • 0299 Other Physical Sciences
  • 0204 Condensed Matter Physics