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Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits

Publication ,  Journal Article
Xiao, H; Hu, X; Gao, T; Zhou, Y; Duan, S; Chen, Y
Published in: IEEE Transactions on Circuits and Systems II: Express Briefs
January 1, 2024

As neural network models are developed and optimized, the use of neural networks in edge devices is increasing, where low-bit neural networks, such as binary neural networks and mixed-precision neural networks, are ideal for edge AI applications. Peripheral circuits and in-memory computing macro are the main components for deploying low-bit precision neural networks on edge AI. However, existing peripheral circuits, including communication units, control modules and analog-to-digital converters (ADCs), are implemented by software or mixed-signal circuits, resulting in significant power and area overheads. To address this issue, memristor-based reconfigurable circuits are proposed for a fully analog implementation of low-bit neural networks without ADCs. In addition, a memristor-based mixed-precision network with a variety of mixed-precision modes is illustrated to verify the effectiveness of deploying low-bit neural networks on edge devices based on the proposed circuits. Furthermore, hybrid simulation results demonstrate that the proposed memristor-based mixed-precision network achieves 84.8∼87.5 % accuracy on the CIFAR-10 dataset, and the parameter scale of the network model is reduced by 1.6∼20x. The circuit analysis demonstrated that the proposed circuits are accurate, robust, and energy-efficient with varying mixed precision, providing a promising and universal solution for applying low-bit neural networks on edge devices.

Duke Scholars

Published In

IEEE Transactions on Circuits and Systems II: Express Briefs

DOI

EISSN

1558-3791

ISSN

1549-7747

Publication Date

January 1, 2024

Volume

71

Issue

1

Start / End Page

66 / 70

Related Subject Headings

  • Electrical & Electronic Engineering
  • 4009 Electronics, sensors and digital hardware
  • 4006 Communications engineering
  • 0906 Electrical and Electronic Engineering
 

Citation

APA
Chicago
ICMJE
MLA
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Xiao, H., Hu, X., Gao, T., Zhou, Y., Duan, S., & Chen, Y. (2024). Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits. IEEE Transactions on Circuits and Systems II: Express Briefs, 71(1), 66–70. https://doi.org/10.1109/TCSII.2023.3298910
Xiao, H., X. Hu, T. Gao, Y. Zhou, S. Duan, and Y. Chen. “Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits.” IEEE Transactions on Circuits and Systems II: Express Briefs 71, no. 1 (January 1, 2024): 66–70. https://doi.org/10.1109/TCSII.2023.3298910.
Xiao H, Hu X, Gao T, Zhou Y, Duan S, Chen Y. Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits. IEEE Transactions on Circuits and Systems II: Express Briefs. 2024 Jan 1;71(1):66–70.
Xiao, H., et al. “Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits.” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 1, Jan. 2024, pp. 66–70. Scopus, doi:10.1109/TCSII.2023.3298910.
Xiao H, Hu X, Gao T, Zhou Y, Duan S, Chen Y. Efficient Low-Bit Neural Network With Memristor-Based Reconfigurable Circuits. IEEE Transactions on Circuits and Systems II: Express Briefs. 2024 Jan 1;71(1):66–70.

Published In

IEEE Transactions on Circuits and Systems II: Express Briefs

DOI

EISSN

1558-3791

ISSN

1549-7747

Publication Date

January 1, 2024

Volume

71

Issue

1

Start / End Page

66 / 70

Related Subject Headings

  • Electrical & Electronic Engineering
  • 4009 Electronics, sensors and digital hardware
  • 4006 Communications engineering
  • 0906 Electrical and Electronic Engineering