Accurate chip scale topography modeling in O(n) run time
Currently, semiconductor manufacturing topography models for design and process optimization can investigate only a tiny portion of a die at a given time. Therefore, important coupling effects between areas are ignored. As interconnect capacitance and resistance become the limiting factor to chip speed, the coupling effects of process variations upon timing delays will become critical. Additionally, current process models are unable to consider known die scale effects such as stepper lens aberrations, tilt, scaling, polishing variations and etch loading effects. We are introducing a model for accurately simulating die scale effects upon semiconductor topography in O(n) run time, where n is the number of mask features, and with efficient memory usage. The inherently parallel model combines existing process models with new developments. The model provides a better interface between design and process areas for complete die performance optimization studies.
